92 Commits

Author	SHA1	Message	Date
James E. Stine	2c140679e3	Minor cosmetic update to fpu.sv	2021-06-01 15:45:32 -04:00
Ross Thompson	8e330367ac	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
Katherine Parry	0646e08609	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
Katherine Parry	65eca433b6	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	bd05de0dbb	FADD and FSUB imperas tests pass	2021-05-26 12:33:33 -04:00
James E. Stine	e3b3321f91	delete old file for FPregfile	2021-05-26 09:13:09 -05:00
James E. Stine	cc2a7ced7f	Add regression test for fpadd	2021-05-26 09:12:37 -05:00
Katherine Parry	3869a73a9c	renamed top level FPU wires	2021-05-25 20:04:34 -04:00
James E. Stine	e32e812f6a	Update FPregfile to use more compact code and better structure for ease in reading	2021-05-25 13:21:59 -05:00
Katherine Parry	03aea055fa	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
James E. Stine	194c32defa	Update header for FPadd	2021-05-24 08:28:16 -05:00
Katherine Parry	55f22979ca	FSD and FLD imperas tests pass	2021-05-23 18:33:14 -04:00
Katherine Parry	71e4a10efb	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
Katherine Parry	409438bc95	floating point infinite loop removed from imperas tests	2021-05-18 10:42:51 -04:00
Katherine Parry	3f05e31954	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00
Katherine Parry	9252d08b41	fpu imperas tests run	2021-05-01 02:18:01 +00:00
Thomas Fleming	c055ab272d	Clean up lint errors in fpu and muldiv ... booth.sv had an actual error where a signal was being assigned to too many bits. muldiv has a lot of non blocking assignments, so I suppressed those warnings so the linter output was readable.	2021-04-22 15:36:03 -04:00
Teo Ene	008b308b79	Fixed most relevant remaining synthesis compilation warnings with Ben	2021-04-21 16:06:27 -05:00
Katherine Parry	204e5cb018	fixed synth bugs in fpu	2021-04-19 00:39:16 +00:00
Katherine Parry	0bdd3efdd5	integraded the FMA into the FPU	2021-04-15 18:28:00 +00:00
Katherine Parry	e075dc2d13	Various bugs fixed in FMA	2021-04-13 18:27:13 +00:00
Teo Ene	0bffac2c74	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
Katherine Parry	08f45eb076	fixed FPU lint warnings	2021-04-08 18:03:21 +00:00
Katherine Parry	ebf4915440	fixed FPU lint warnings	2021-04-08 17:55:25 +00:00
Katherine Parry	f41b5a2d38	Added missing files in FPU	2021-04-04 18:09:13 +00:00
Katherine Parry	08b31f7b2a	Integrated FPU	2021-04-03 20:52:26 +00:00
Brett Mathis	aedc96cd04	FPU Pipeline completed - can begin integration	2021-03-25 13:29:03 -05:00
Katherine Parry	123e63b440	fixed various bugs in the FMA	2021-03-24 21:51:17 +00:00
Katherine Parry	fb78dedae2	fixed various bugs in the FMA	2021-03-24 01:35:32 +00:00
Katherine Parry	9af0ad815c	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Katherine Parry	fd381e60d7	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
Katherine Parry	5374dca1b9	fixed various bugs	2021-03-04 22:20:39 +00:00
Katherine Parry	4591b25c86	fixed various bugs	2021-03-04 22:20:28 +00:00
Katherine Parry	6fa2bc8efe	fixed various bugs	2021-03-04 22:20:23 +00:00
Katherine Parry	10b179399c	fixed various bugs	2021-03-04 22:20:02 +00:00
Katherine Parry	8e3b74c772	fixed various bugs	2021-03-04 22:19:21 +00:00
Katherine Parry	4e6b35c8b2	fixed various bugs	2021-03-04 22:18:47 +00:00
Katherine Parry	3c86d0912a	fixed various bugs	2021-03-04 22:18:19 +00:00
David Harris	1b61d78ac2	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
Brett Mathis	b0a5052bcf	FPU Assembly tests	2021-02-25 14:32:36 -06:00
Katherine Parry	906ec30339	inital FMA push	2021-02-23 20:19:12 +00:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00