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Author SHA1 Message Date
James E. Stine
a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Skylar Litz
5bcae393c9 added delayed MIP signal 2021-10-04 18:23:31 -04:00
kipmacsaigoren
b72e94badf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
Ross Thompson
047bbcf3d7 updated fpga wavefile. 2021-10-03 12:14:22 -05:00
Ross Thompson
e9135f1fd5 Added fpga wave file. 2021-10-03 11:56:11 -05:00
Ross Thompson
8653a87e24 Added more debug flags. 2021-10-03 11:41:21 -05:00
David Harris
36bbf0c502 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
10ef563211 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
78eba19a1f Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
48e33c79a9 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
648cc8ef64 Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
d468357c24 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:43:47 -04:00
David Harris
81601e26a3 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
c690a863b5 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
7fdb0158d4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
bb868f7a37 checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
0c08a7c05c More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
5e6b2490cb Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
418e9cd6e6 Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
5db800fac3 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
3a85c972b6 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
5d64f04752 Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
f913305993 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
afd6babc13 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
e33ef58e67 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
4926ae343a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
852eb24731 Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
9d63aa683f Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
fbe6e41169 Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit fec96218f6.
 2021-09-30 20:45:26 -04:00
David Harris
caa36f267d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
9d8e7f2714 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
760f4d66dd RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
Ross Thompson
fca9b9e593 Movied tristate to test bench level. 2021-09-30 11:27:42 -05:00
Ross Thompson
cefbcd1b0c Partially sd card read on fpga. 2021-09-30 11:23:09 -05:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
fec96218f6 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
a835572836 first attemtpt at checkpoint infrastructure 2021-09-28 22:33:47 -04:00
Ross Thompson
7ca801113e Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
bbracker
7117c0493c condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
Ross Thompson
7d749b201b added support to due partial fpga simulation. 2021-09-26 15:00:00 -05:00
Ross Thompson
4d1b02c068 Merge branch 'main' into fpga 2021-09-26 13:22:53 -05:00
Ross Thompson
3a9bc1e8c1 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 
the flash card to dram.
Fixed latch issue in the sd card reader.
 2021-09-26 13:22:23 -05:00
Ross Thompson
af53657eaf Merge branch 'sdc' into fpga 2021-09-25 19:33:07 -05:00
Ross Thompson
a213ecbdb2 GPIO marker to indicate the sdc to dram transfer complete. 2021-09-25 19:29:15 -05:00
Ross Thompson
c917f14b6b Almost done writting driver for flash card reader. 2021-09-25 19:05:07 -05:00
Ross Thompson
69674f272a We now have a rough sdc read routine. 2021-09-25 17:51:38 -05:00