11 Commits

Author	SHA1	Message	Date
Thomas Fleming	f9bf2fbc01	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Thomas Fleming	ca2a65770c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Thomas Fleming	e48dc38869	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Noah Boorstin	0af002eb2f	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
kaveh pezeshki	e8b306bcba	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
Noah Boorstin	43f9abdbed	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
Noah Boorstin	c03f69fb80	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00