15 Commits

Author	SHA1	Message	Date
Ross Thompson	b0aea77b20	Added generate around uncore.	2022-08-25 10:35:24 -05:00
Ross Thompson	01a7718471	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	fc22e807e2	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Ross Thompson	d83db2cde5	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
Ross Thompson	57eba4355e	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
Ross Thompson	a440bc2ac5	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
Ross Thompson	de0bef4f5b	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	f7f3882cb8	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	d9e8d16bbe	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00