13 Commits

Author	SHA1	Message	Date
Ross Thompson	12b978fec2	Eliminated extra register and fixed ports to icache. ... Still need to support physical tag check and write in icache memory. Still need to reduce to 1 port SRAM in icache. I would like to refactor the icache code.	2021-05-03 12:04:54 -05:00
Ross Thompson	50e893eec9	Fixed for the instruction spills.	2021-04-21 16:47:05 -05:00
Ross Thompson	daa1ab9261	Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.	2021-04-20 21:19:53 -05:00
Jarred Allen	3868a82932	dcache lints	2021-04-15 21:13:56 -04:00
Jarred Allen	c32fe09056	More icache bugfixes	2021-04-14 19:03:33 -04:00
Jarred Allen	757b64e487	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/cache/dmapped.sv wally-pipelined/src/cache/line.sv wally-pipelined/src/ifu/icache.sv	2021-04-14 18:24:32 -04:00
Teo Ene	0bffac2c74	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
Jarred Allen	357aed75ee	A few more cache fixes	2021-04-13 01:07:40 -04:00
Jarred Allen	8dc57a7706	Begin changes to direct-mapped cache	2021-04-01 13:55:21 -04:00
ushakya22	ba01d57767	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Jarred Allen	0776127c75	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
Jarred Allen	abf9f3b3cb	Fix compile errors from const not actually being constant (why does Verilog do this)	2021-03-24 00:58:56 -04:00
Jarred Allen	ebd2c60b74	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00