19 Commits

Author	SHA1	Message	Date
Ross Thompson	f2c1ca4bd5	added support to due partial fpga simulation.	2021-09-26 15:00:00 -05:00
Ross Thompson	d4f514010d	Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.	2021-09-22 10:54:13 -05:00
David Harris	b5df9b282d	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
Kip Macsai-Goren	1485d29dde	Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.	2021-06-24 20:01:11 -04:00
David Harris	c3d106f0f0	Removed two cycles of latency from the DTIM	2021-06-10 10:30:24 -04:00
David Harris	9dd3857c26	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
Ross Thompson	7f12c7af90	Switch to use RV64IC for the benchmarks. ... Still not working correctly with the icache. instr addr correct got	2021-04-07 19:12:43 -05:00
bbracker	d52c71086a	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
bbracker	df51d9908d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	63bfd79009	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
David Harris	fe4d288589	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
bbracker	62dd9e3075	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	cfcd7d1518	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	b3247eadd2	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	2769b147cb	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9f9c3bcece	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00