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Author SHA1 Message Date
David Harris
4edf9b6355 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
1aa3e65bae Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
e2e63ca9a8 Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
545d46acb9 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
d353cef432 Removed unused ch5 assembly example 2022-05-12 14:05:27 +00:00
David Harris
1e7401daa0 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
999754801c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
6cba6a92ba filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
aa452b2f38 Moved some privileged tests to be simulated. 2022-05-12 04:45:41 +00:00
David Harris
9999f69922 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
b2c921ee7b Added examples/asm/trap trap handler example 2022-05-12 04:31:00 +00:00
David Harris
9dd378098f merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
1f761c4e06 PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
552a55d631 ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
mmasserfrye
6fad0dc8ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-11 16:16:23 +00:00
mmasserfrye
68da2f5fa1 modified ppa.sv to match module name and added madzscript 2022-05-11 16:13:01 +00:00
David Harris
8166fd772e Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
137b411bea Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
490902a655 Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
bb24aebebd Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
04fd22aeb0 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
1a5bfcf078 Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
a516f89f22 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
412d4656ed Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
7f42ff06d2 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
f436e93fc5 SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
1a7599ce94 Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
7249879a74 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
99423993a9 added explicit clears to mstatus.mie 2022-05-04 23:00:17 +00:00
Kip Macsai-Goren
536df2b8ad Updated test libraries to reflect variable name changes 2022-05-04 21:39:36 +00:00
Kip Macsai-Goren
35e619ae74 renamed test_loop_setup to run_test_loop 2022-05-04 21:39:09 +00:00
Kip Macsai-Goren
26dfe36c16 renamed debug to extended signature 2022-05-04 21:38:37 +00:00
Kip Macsai-Goren
b155effe66 put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
895a4f4832 updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
a9a434fced removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
f36fdf940d removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
badbe0840f renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
David Harris
8a43d6099b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
4b91fddc0a Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
b4a422f771 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00