Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Jarred Allen
bd8f1eea3c
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974
Fix another bug in icache
2021-04-06 12:48:42 -04:00
Jarred Allen
c95da7d11e
Fix bug in icache
2021-04-03 18:10:54 -04:00
Shreya Sanghai
df149d1be7
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
ShreyaSanghai
28a9c6ba56
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
Shreya Sanghai
b544526766
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Ross Thompson
9172e52286
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Ross Thompson
2a308309e4
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Jarred Allen
7ca57cc4fc
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
Noah Boorstin
b5a1691c2b
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb
Merge branch 'PPA' into main
...
Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
ShreyaSanghai
139c2076a1
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Brett Mathis
162f2df880
FPU Pipeline completed - can begin integration
2021-03-25 13:29:03 -05:00
Jarred Allen
b774d35c34
Output NOP instead of BAD when reset
2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/uncore/dtim.sv
2021-03-25 12:10:26 -04:00
Thomas Fleming
e3900bd0fa
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-25 02:35:21 -04:00
bbracker
a3788eb218
added 1 tick delay to dtim flops
2021-03-25 02:23:30 -04:00
bbracker
b5fa410e15
added 1 tick delay on tim reads
2021-03-25 02:15:28 -04:00
Jarred Allen
682050a33b
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-03-25 00:51:12 -04:00
bbracker
67b27cd2f5
instrfault direspecting stalls bugfix
2021-03-25 00:44:35 -04:00
bbracker
02e924e55a
instrfaults not respecting stalls bugfix
2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d
upgraded gpio bus interface
2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc
future work comment about suspicious-looking verilog in csri.sv
2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822
Add all PMP addr registers
2021-03-24 21:58:33 -04:00
Katherine Parry
18cb1f4873
fixed various bugs in the FMA
2021-03-24 21:51:17 +00:00
Ross Thompson
a99c0502e5
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Jarred Allen
c1fe16b70b
Give some cache mem inputs a better name
2021-03-24 12:31:50 -04:00
Jarred Allen
a51257abca
Fix compile errors from const not actually being constant (why does Verilog do this)
2021-03-24 00:58:56 -04:00
Ross Thompson
1c6e37120e
Fixed RAS errors. Still some room for improvement with the BTB and RAS.
2021-03-23 23:00:44 -05:00
Jarred Allen
4410944049
Merge branch 'main' into cache
2021-03-23 23:35:36 -04:00
Ross Thompson
84ad1353e4
Fixed a bunch of bugs with the RAS.
2021-03-23 21:49:16 -05:00
Katherine Parry
56dc8de009
fixed various bugs in the FMA
2021-03-24 01:35:32 +00:00
Ross Thompson
4fb7a1e0a6
Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 16:53:48 -05:00
Jarred Allen
d6ecc3ede0
Begin work on direct-mapped cache
2021-03-23 17:03:02 -04:00
Teo Ene
ef3d2dda48
Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
2021-03-23 15:21:13 -05:00
Shreya Sanghai
1d6a2989ed
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Jarred Allen
0f8fe8fb3b
Document some internal signals
2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d
Add comments explaining icache inputs
2021-03-23 00:07:39 -04:00
Jarred Allen
827993598d
Small commit to see if new hook tests non-main branch
2021-03-22 23:57:01 -04:00
Noah Boorstin
15474f678d
Merge branch 'main' into cache
2021-03-22 23:28:30 -04:00
bbracker
5efd5958e7
added delays to uart AHB signals
2021-03-22 15:40:29 -04:00
Jarred Allen
6ce52f9b80
Remove DelaySideD since it isn't needed
2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714
Update icache interface
2021-03-22 15:04:46 -04:00
Jarred Allen
3748d03adc
Merge branch 'main' into cache
2021-03-22 13:47:48 -04:00
