Github_Repos/cvw
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2,127 Commits 4 Branches 2 Tags 53 MiB
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5 Commits

Author SHA1 Message Date
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
Ross Thompson
3b8bdc7b2d Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Ross Thompson
5fdac9fa3b Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
2e0dcaaff9 Fpga simualtion files. 2021-10-11 10:24:40 -05:00