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2163 Commits

Author SHA1 Message Date
Ross Thompson
56a24d02e8 Fixed subtle bug in btb. 2023-01-25 15:16:53 -06:00
Ross Thompson
16142eca59 Added logic to forward btb prediction results. 2023-01-25 13:02:20 -06:00
Ross Thompson
4550966678 More btb cleanup. 2023-01-25 12:14:18 -06:00
Ross Thompson
40b4811d2b Found minor bug in gshare. 2023-01-25 12:08:54 -06:00
Ross Thompson
afdcfeb93b BTB cleanup. 2023-01-25 12:05:13 -06:00
Ross Thompson
7e1363bfad Optomized gshare. 2023-01-25 11:41:16 -06:00
Ross Thompson
b931110f2d Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
ad6f7041b4 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
56369f7641 Removed old versions of gshare. 2023-01-24 17:26:54 -06:00
Ross Thompson
1acbdaeca6 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
1170dc7250 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7d1109fc24 Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
2157970adf Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
David Harris
490ca23c87 Merge remote-tracking branch 'upstream/main' into dev 2023-01-24 09:40:07 -08:00
David Harris
f28b0e5c1a bpred input spacing cleanup 2023-01-24 06:14:31 -08:00
David Harris
5233117568 bpred tab cleanup 2023-01-24 05:42:34 -08:00
Ross Thompson
5494ee2159 Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
a4d5ccc4d6 Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
1439ff02c7 Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e9f435bbda Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
af6899472d Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
fc6cf1f198 formatting 2023-01-23 10:54:06 -08:00
David Harris
2d7f39672a Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
626bcd8608 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
45218863af test 2023-01-20 15:23:38 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
a968ae2f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
e87c2b2724 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
0123776037 Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
2e9b5f9ae4 Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
bcadbd7104 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
ecceea177a Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
3d202ed2fd Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
d3df8e062e Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
1ecf4e4cc9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
74ab386735 More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
26cb45e240 renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
29f45d6203 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
2cca457f14 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
da4eec7e0e Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
23ab178192 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
928e06d4fa Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
569a016efa Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
0488723db9 Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
9df5fdbd89 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
25b607566c RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
b027921902 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
ea96c2375f Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
e380fd71ff Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
d9d5b99218 update 2023-01-19 13:29:46 +00:00
Ross Thompson
47fdff6488 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
49daa736b1 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
cd2f7c6208 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
7289fa8d44 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
026d09b79b More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
19e4d0f7cd Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
997dda11a8 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
fb234d506d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
469efa61af Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cbf46f417a Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
22eee73a45 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
2048edb7a0 Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
40c0e67930 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
2622f5dfb8 Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
a6b14eb9ee Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
0b244e289c Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
affca27ec4 Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
58a07399a2 Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
fc5424fa62 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
607c64e0ee Formating. 2023-01-18 16:52:46 -06:00
Ross Thompson
c34acab1d7 Formating. 2023-01-18 16:47:40 -06:00
David Harris
915987c524 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-18 13:07:03 -08:00
David Harris
331ef80d0f removed fma directory, improved plic comments 2023-01-18 13:06:54 -08:00
eroom1966
7c0cad148d Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61 changes made with Ross 2023-01-18 16:46:48 +00:00
sarah-harris
789fc0e493 Minor fixes in datapath.sv and ieu.sv (comments, putting signals in correct grouping) 2023-01-18 07:26:08 -08:00
eroom1966
a5a5b7a408 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
df4419dea2 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
eroom1966
c18942bd0b refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
a929e53576 More comments added to abhfsm. 2023-01-17 22:58:06 -06:00
Ross Thompson
4bfabc4136 formating ahbinterface. 2023-01-17 22:54:42 -06:00
Ross Thompson
4b47598138 Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
8f4f17a4c8 Added commenets and formating to abhcachefsm and abhcacheinterface. 2023-01-17 22:22:23 -06:00
Ross Thompson
f146a01344 Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
d6c80d937c Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
c75a164f46 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
Ross Thompson
97661a023a Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 21:54:55 -06:00
Ross Thompson
b30c13a188 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
aa942feedc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
c73bea83cd Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
caff6e788c Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
Ross Thompson
c6e366b86e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 14:50:45 -06:00
David Harris
555fee94fa IEU comment cleanup 2023-01-17 10:51:44 -08:00
David Harris
77766a6dac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-17 06:47:06 -08:00
David Harris
c8d77d785c IEU signal comment cleanup 2023-01-17 06:47:02 -08:00
sarah-harris
4e9a7a6403 Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
David Harris
15866cb11d pipelined/src/ieu/ieu.sv 2023-01-17 06:08:26 -08:00
sarah-harris
cb153d74d9 IEU cleanup 
IEU cleanup
 2023-01-17 06:02:26 -08:00
eroom1966
8caa93ce4d refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
f4e7e54abe Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
c65becbae5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-16 14:03:05 -06:00
Ross Thompson
7c4eaa1ca6 Found a potential issue with mstatush when XLEN = 64. 2023-01-16 13:57:28 -06:00
Ross Thompson
fabe13bdce Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
f93b7cfda7 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
12e12e464a Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
David Harris
7f68a55b8c Clean up tabs 2023-01-15 18:23:09 -08:00
Ross Thompson
8a0e38fd92 Fixed bug with gshare repair from branch class miss prediction. 2023-01-15 14:39:48 -06:00
David Harris
56dac4be7d cache cleanup 2023-01-14 19:43:29 -08:00
David Harris
08fca1c517 ebu cleanup 2023-01-14 19:29:45 -08:00
David Harris
a6d8511a2e ebu cleanup 2023-01-14 19:19:34 -08:00
David Harris
91afe5522b generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
9c79078be1 generic cleanup 2023-01-14 18:56:46 -08:00
David Harris
93b0286934 mmu cleanup 2023-01-14 18:27:53 -08:00
David Harris
9d51abc2e1 mmu cleanup 2023-01-14 18:20:47 -08:00
David Harris
ee1b4fe221 mmu cleanup 2023-01-14 18:14:38 -08:00
David Harris
7c5548a39c mmu cleanup 2023-01-14 17:49:10 -08:00
David Harris
939bf3f148 mmu cleanup 2023-01-14 17:35:21 -08:00
David Harris
697a8d8f50 uncore cleanup 2023-01-14 17:21:07 -08:00
David Harris
a4c753635e uncore cleanup 2023-01-14 17:09:11 -08:00
David Harris
a2b455d7b5 uncore cleanup 2023-01-14 17:07:36 -08:00
David Harris
f16267ddbc uncore cleanup 2023-01-14 17:00:58 -08:00
David Harris
1ec42b9d50 sdc cleanup 2023-01-14 16:49:44 -08:00
David Harris
3ad4ae352c uncore cleanup 2023-01-14 06:15:35 -08:00
David Harris
0c91505f41 Wallypipeliendcore/soc cleanup 2023-01-14 05:57:50 -08:00
David Harris
10f76dd7e6 csr & wally cleanup 2023-01-13 22:25:19 -08:00
David Harris
efe7e88258 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
90e7aa2d50 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
9526479782 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
c9c174de49 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
be236d9438 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
50415a0a12 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
25d8566694 csr comments 2023-01-13 20:49:34 -08:00
David Harris
543d9d379b trap comments 2023-01-13 19:50:44 -08:00
David Harris
b613722617 trap comments 2023-01-13 19:44:38 -08:00
David Harris
74d3e0aa40 privileged comments 2023-01-13 17:57:38 -08:00
Ross Thompson
4c78bcade8 Possible improvement to gshare. 2023-01-13 18:50:01 -06:00
Ross Thompson
76a9e7d963 Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
886e4e2935 Partial fix to RAS prediction accurracy. 2023-01-13 18:05:47 -06:00
Ross Thompson
4aa2b5737f Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
0e215ac3c6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
de7f3b14fc More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
55169fa9b0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-13 10:26:07 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00