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Author SHA1 Message Date
Ross Thompson
ffc5bce0b6 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679 Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
d15cf5c65c Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
1463e9b1d4 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
6f01ea12e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
38adcb5b17 Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
f486a763d9 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
033f844d09 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
9ee2d84c7c Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6c0ef05db commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
1d268fded4 added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
ae32e2a9ee added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
7411d50a78 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
badc684f07 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
9806babe9e Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
0fdbfb87eb Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
85366a287b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-05 17:20:12 -06:00
Ross Thompson
bcb927d172 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
rachanaerra
4f042b0adb updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
2bcaacb179 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
b84b709182 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
e1ac736d43 Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
Ross Thompson
b7d004b261 Removed old flow directory. 2022-12-03 10:28:39 -06:00
Ross Thompson
ec8ae6e3a8 removed imperas-riscv-tests-deleteme 2022-12-03 00:18:42 +00:00
Ross Thompson
d969ae35e5 removed unusedsrc directory as it was large 384MB! 2022-12-02 17:37:06 -06:00
Ross Thompson
9d960dec65 Removed design ware mult. 2022-12-02 16:51:12 -06:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
01028e7088 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
4c6003d9e2 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
33e4361de5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
8afc054e74 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
ed39099405 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
1d9b5badee Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
f64c0589fe FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
da92cdccd0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
cb310bfb1d Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
558f0b655e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00