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638 Commits 5 Branches 2 Tags 53 MiB
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557 Commits

Author SHA1 Message Date
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
35f8b4f74f Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
ushakya22
99f2d24e05 Latest IE tests with timer interupts 2021-04-08 17:53:39 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
1ee8feffe5 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
005f838b8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
755e2e5771 merge testbench 2021-04-08 14:28:01 -04:00
Katherine Parry
b7ebfd66ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:06:51 +00:00
David Harris
8549e457c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:04:09 -04:00
David Harris
6b2868a8c7 restored testbench-imperas.sv 2021-04-08 14:04:01 -04:00
Katherine Parry
2ee015d53e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:03:57 +00:00
Katherine Parry
f4cb92ae71 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
ushakya22
72a64edfb8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 13:55:23 -04:00
ushakya22
b0f6898ece Updates to WALLY-IE tests 2021-04-08 13:54:42 -04:00
David Harris
ac8a111d61 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
6a6ccca3c8 fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
Noah Boorstin
14d2ad1e2d try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
3067e94b4b Update privileged testgen & helper script 2021-04-08 05:14:07 -04:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
fc39535e4e Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
c54aecde73 Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
ushakya22
83d9aa3a50 MIE privilege tests with working timer interupt 2021-04-07 04:09:09 -04:00
Domenico Ottolia
60cf38192b Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Noah Boorstin
284d583877 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
38017e6aae declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202 plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38 Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
f4e5642c62 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Thomas Fleming
1cbdaf1f05 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
d21006d048 Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6 Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
0595ae983f Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
bfb4b051c6 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
5afb255251 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
Teo Ene
7c364a26e9 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Noah Boorstin
75f58c4df5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Thomas Fleming
77b8e27205 Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
56e256baa5 Extend lint-wally to lint both rv32 and rv64 2021-03-30 22:42:28 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
61b19a0cd0 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
351c71e812 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
fbed5d658e privilege tests 2021-03-30 15:23:47 -04:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
Jarred Allen
39bf2347bc Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Noah Boorstin
05d362e334 regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
56a32b5882 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
0290568a52 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
David Harris
eb9787609e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
ce6f102fc5 Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
128278ea27 Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
ba95557c44 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
ebd6b931c6 Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
51291949d8 Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
a8abd47fbc Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00