9 Commits

Author	SHA1	Message	Date
Kip Macsai-Goren	c1c564d54c	added changes to priority encoders from synthesis branch (correctly this time I hope)	2021-07-19 15:06:14 -04:00
David Harris	4d53a935b3	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
David Harris	6dc49dd073	Renamed tlb ReadLines to Matches	2021-07-07 06:32:26 -04:00
David Harris	087bed3b67	Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines	2021-07-06 10:38:30 -04:00
David Harris	6b9cfe90d8	Added ASID & Global PTE handling to TLB CAM	2021-07-04 17:52:00 -04:00
David Harris	d138d6545d	Restructured TLB Read as AND-OR operation with one-hot match/read line	2021-07-04 17:01:22 -04:00
David Harris	b59213c83f	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
Kip Macsai-Goren	e044f72e59	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
Kip Macsai-Goren	146ed95bdb	got rid of some underscores in filenames, modules	2021-06-07 18:54:05 -04:00