David Harris
|
bf54c1c868
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:29:20 -07:00 |
|
Ross Thompson
|
21526957cf
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
96d6218078
|
Possible reduction of ignorerequest.
|
2022-08-19 18:07:44 -05:00 |
|
Ross Thompson
|
5301444a61
|
Changed signal names.
|
2022-08-17 16:12:04 -05:00 |
|
Ross Thompson
|
970a90dd72
|
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
|
2022-08-17 16:09:20 -05:00 |
|
Ross Thompson
|
c3bd396bdb
|
Removed old code from interlockfsm.
|
2022-08-17 12:52:56 -05:00 |
|
Ross Thompson
|
f7e64fcd69
|
Fixed fstore2 in cache?
|
2022-08-01 22:04:44 -05:00 |
|
Ross Thompson
|
b8356c7449
|
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
|
2022-08-01 21:12:25 -05:00 |
|
Ross Thompson
|
171cf7413b
|
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
|
2022-08-01 21:08:14 -05:00 |
|
Ross Thompson
|
5d9dab6149
|
pulled swbbytemask out of subword write.
|
2022-08-01 20:48:45 -05:00 |
|
Ross Thompson
|
f1bd2524b7
|
Don't use this commit yet. Untested.
|
2022-07-24 15:40:52 -05:00 |
|
Ross Thompson
|
334008630f
|
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
|
2022-07-24 01:20:29 -05:00 |
|
Ross Thompson
|
5cd6c8069d
|
signal name cleanup.
|
2022-07-22 23:36:27 -05:00 |
|
Katherine Parry
|
452b017f9a
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
ca4fe08fd9
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
David Harris
|
d73645944f
|
APB CLINT passing regression
|
2022-07-05 15:51:35 +00:00 |
|
Katherine Parry
|
6baded9121
|
added rv32 double precision stores - untested
|
2022-06-28 21:33:31 +00:00 |
|
Katherine Parry
|
254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
slmnemo
|
98c07ce2c0
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
|
slmnemo
|
3d715a098c
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
|
slmnemo
|
cadd62e49f
|
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
|
2022-06-10 20:43:56 -07:00 |
|
slmnemo
|
beb4317e68
|
Added comments to signals added so the bus is easier to analyze
|
2022-06-10 20:30:04 -07:00 |
|
slmnemo
|
b7357efc6b
|
Fixed failed regression state by only enabling counting when doing cached operations
|
2022-06-10 20:00:09 -07:00 |
|
slmnemo
|
63ed390c90
|
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
|
2022-06-10 19:10:01 -07:00 |
|
slmnemo
|
dc11066ff2
|
Passed Regression: Seems to work perfectly fine
|
2022-06-09 18:21:13 -07:00 |
|
slmnemo
|
5a6eae214a
|
?
|
2022-06-09 17:50:47 -07:00 |
|
slmnemo
|
3e8d3bae88
|
Changes made on 9th Jun
|
2022-06-09 17:33:51 -07:00 |
|
slmnemo
|
0d04751c77
|
Fixed error when doing uncached accesses where HTRANS was always 2
|
2022-06-08 18:58:07 -07:00 |
|
slmnemo
|
81d373c7ab
|
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
|
2022-06-08 17:34:02 -07:00 |
|
slmnemo
|
315c2f0669
|
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
|
2022-06-08 15:29:32 -07:00 |
|
slmnemo
|
054cf5f7b0
|
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
|
2022-06-08 15:03:15 -07:00 |
|
slmnemo
|
284e0395a0
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
slmnemo
|
2d76953d42
|
Added lock signal to ensure AHB speaks with the right bus
|
2022-06-08 02:19:21 +00:00 |
|
slmnemo
|
6d36150c3d
|
Fixed off-by-one error in busdp capture
|
2022-06-07 19:36:39 +00:00 |
|
slmnemo
|
73e0c1c07f
|
Reworked bus to handle burst interfacing
|
2022-06-07 11:22:53 +00:00 |
|
David Harris
|
c7ec9282fe
|
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
|
2022-06-02 14:18:55 +00:00 |
|
slmnemo
|
446ad498aa
|
Fixed double assignment on LSUBurstType
|
2022-06-01 01:04:49 +00:00 |
|
slmnemo
|
bc17f883d4
|
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
|
2022-05-26 18:41:27 -07:00 |
|
slmnemo
|
847c7930c4
|
added LSUBurstDone signal to signal when a burst has finished
|
2022-05-26 16:29:13 -07:00 |
|
slmnemo
|
80fc716cd7
|
Added signal to monitor HBURST and comments for each burst in busdp
|
2022-05-26 13:35:49 -07:00 |
|
slmnemo
|
08430a1e85
|
added burst size signals to the IFU, EBU, LSU, and busdp
|
2022-05-25 18:02:50 -07:00 |
|
David Harris
|
5670f77de2
|
More unused signal cleanup
|
2022-05-12 15:21:09 +00:00 |
|
David Harris
|
e2e63ca9a8
|
Clean up unused signals
|
2022-05-12 14:49:58 +00:00 |
|
David Harris
|
04fd22aeb0
|
endian swapper
|
2022-05-08 06:51:50 +00:00 |
|
David Harris
|
4f1b0fdc64
|
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
|
2022-05-08 06:46:35 +00:00 |
|
David Harris
|
22842816a8
|
LSU name cleanup
|
2022-04-18 03:18:38 +00:00 |
|
David Harris
|
c07b9d1722
|
Renamed FinalAMOWriteDataM to AMOWriteDataM
|
2022-04-18 01:30:03 +00:00 |
|
David Harris
|
d8b4c985cd
|
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
|
2022-04-17 22:33:25 +00:00 |
|
Ross Thompson
|
bfc68bef69
|
Fixed possible bugs in LRSC.
|
2022-04-16 14:45:31 -05:00 |
|