Ross Thompson
cc48cdc97b
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
Ross Thompson
f93eaeef8e
Fixed another bug with the speculative gshare with instruction class prediction.
2023-01-29 00:33:40 -06:00
Ross Thompson
6371d91b37
Added another performance counter to track overall branch miss-predictions.
2023-01-28 17:50:46 -06:00
Ross Thompson
8a277f6b75
Possible fix for speculative gshare.
2023-01-28 16:14:19 -06:00
Ross Thompson
a212960352
Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction.
2023-01-27 11:34:45 -06:00
Ross Thompson
4fa2dcc2a5
Changed the performance counters to track different data.
...
Now rather than tracking jump(r) we track jump(r) and taken branches.
2023-01-26 13:21:28 -06:00
Ross Thompson
3dc441ff8c
Intermediate commit. Passes regression tests, but RAS is not correct.
2023-01-25 19:39:18 -06:00
Ross Thompson
5da1aeeef1
Improved RAS again.
2023-01-25 17:10:52 -06:00
Ross Thompson
6cbce9672d
Possibly working speculative global history.
2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3
core part of global history works now. forwarding is still broken.
2023-01-08 23:35:02 -06:00
Ross Thompson
78e441fb38
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
9d03109f34
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
0eceeeeeaa
Simiplified global history branch predictor.
2023-01-04 23:41:55 -06:00
Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
206bc7daa6
Closing in on icache flushed by FlushD rather than TrapM.
2022-12-22 20:19:09 -06:00
Ross Thompson
b1475df5e1
Wavefile updates.
2022-12-22 19:45:02 -06:00
Ross Thompson
a02b40cf02
Changes to wave file.
2022-12-21 08:41:47 -06:00
Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
8692ccbafb
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
8d01cf32fc
Updated wavefile.
2022-10-05 14:55:40 -05:00
Ross Thompson
47e936cab3
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
Ross Thompson
9d5a7281b8
Modified ram_ahb to work with different latencies.
2022-09-04 14:46:15 -05:00
Ross Thompson
fcd1465de1
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
5b8f888e21
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e
Updates to wave file.
2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44
Temporary commit.
2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
5cc4f1f1cd
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90
Added generate around ebu.
2022-08-25 09:24:13 -05:00
Ross Thompson
5301444a61
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
334008630f
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
e12e6c3acd
Added more i-cache signals to wave file.
2022-07-24 00:24:13 -05:00
