59 Commits

Author	SHA1	Message	Date
Shreya Sanghai	74f1641c5a	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	4c8952de6a	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Shreya Sanghai	f0ec365117	added performance counters	2021-03-04 11:42:52 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	a357f2a0e7	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9a51bb27c3	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
David Harris	dc2443c55b	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	1d9c741c00	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	fa18052348	Added test configurations	2021-01-25 11:28:43 -05:00