Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
David Harris
fbee4963da
Converted flops to synchronous reset now that reset signal is synchronized
2021-10-25 11:49:20 -07:00
David Harris
ac1b1bfbb6
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
0dabb6ebd4
lint cleaning and moved files into subdirectories
2021-10-23 08:53:32 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
3bc985d230
Changed some flops to settable
2021-10-18 17:05:29 -07:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
bfe633d087
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
75c17dc372
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
David Harris
0c08a7c05c
More divider cleanup
2021-10-03 00:20:35 -04:00
David Harris
e33ef58e67
Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
2021-10-02 10:36:51 -04:00
David Harris
e11c565a6f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
David Harris
caa36f267d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
a7be88a43b
Changes to make fpga synthesizable.
...
Added preload to test simple program on wally in fpga.
2021-09-22 10:54:13 -05:00
Ross Thompson
be864abcc5
Fixed bug with or_rows.
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If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.
2021-09-11 15:51:11 -05:00
David Harris
118cb7fb87
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
David Harris
3fa55a01f4
simplified or_rows generation and renamed oneHotDecoder to onehotdecoder
2021-08-25 06:46:41 -04:00
David Harris
e3dc59c5a2
renamed or_rows.sv
2021-07-16 20:17:03 -04:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
d78e31e9df
Forgot to include one hot decoder.
2021-07-14 15:46:52 -05:00
David Harris
223086ac33
added or.sv
2021-07-13 13:26:40 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
9645b023c9
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Teo Ene
ec21126474
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
Katherine Parry
75a6097467
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Ross Thompson
e50a1ef5e4
Fixed a few lint errors,
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clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
Ross Thompson
0670c57fd2
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
Ross Thompson
fe22fd2db8
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
James E. Stine
12c34c25f3
Modify elements of generics for LZD and shifter wrote for integer
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divider.
2021-05-31 08:36:19 -04:00
Noah Boorstin
2c25e270a2
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
