Ross Thompson
bbd1332353
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
ee81cfff0c
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
Ross Thompson
6d2a4b8354
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
9886ed3028
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
David Harris
0e9fe6c214
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-14 11:15:58 -08:00
David Harris
2d24230093
ALU and datapath cleanup
2021-12-14 11:15:47 -08:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
2d662bc4be
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-13 17:16:20 -06:00
Ross Thompson
81da8b8d2a
Formating changes to cache fsms.
2021-12-13 17:16:13 -06:00
Ross Thompson
4d6d72a082
Fixed some typos in the dcache ptw interaction documentation.
2021-12-13 15:47:20 -06:00
David Harris
55f3979b67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-13 07:57:49 -08:00
David Harris
2039752740
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
kwan
8f79a12cbb
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea
test
2021-12-13 00:31:51 -08:00
kwan
a365e86197
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
Ross Thompson
051dd7d09d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b
Revert "Privilige .*s removed"
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This reverts commit 82bab8e90e
2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247
Revert "Priviledged .* removed"
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This reverts commit a95efea0b3
2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
545c586186
Added proper credit to Richard Davis, the author of the original sd card reader.
2021-12-12 15:05:50 -06:00
kwan
a95efea0b3
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
82bab8e90e
Privilige .*s removed
2021-12-12 09:54:14 -08:00
David Harris
a7e9dee77d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 05:49:31 -08:00
Ross Thompson
37079626cd
Fixed numerous errors in the preformance counter updates.
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Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
slmnemo
e39f94b645
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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help
2021-12-08 14:09:58 -08:00
slmnemo
f2f15c0495
Removed .* from /wally-pipelined/src/uncore/uart.sv
2021-12-08 14:02:53 -08:00
Ross Thompson
f1ea52cb2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 15:50:43 -06:00
Ross Thompson
741a21d0df
Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
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Remove preload from dtim.
2021-12-08 15:50:15 -06:00
David Harris
bb49ba94a0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 13:48:49 -08:00
David Harris
a1f8f7babe
Refactored IEU/ALU logic
2021-12-08 13:48:04 -08:00
Noah Limpert
5f0521d497
updated fcmp.sv instantiation to remove x*'s
2021-12-08 13:34:33 -08:00
David Harris
e14eb9872e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
David Harris
d936342c97
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
slmnemo
7d614869a1
Removed .*s from wally-pipelined/src/uncore/uncore.sv
2021-12-08 01:03:02 -08:00
slmnemo
f413ea1b4a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 00:26:13 -08:00
Noah Limpert
15bdf5680e
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
slmnemo
021faaf8cd
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Katherine Parry
80f026a734
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
c9808988c1
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
2b41e37160
intentionally breaking commit
2021-12-07 13:23:19 -08:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
