Ross Thompson
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bb5b5e71b1
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Replaced FinalReadDataM with ReadDataM in dcache.
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2021-07-20 13:27:29 -05:00 |
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David Harris
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c117356432
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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James E. Stine
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b36d6fe1be
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slight mod to fpdiv - still bug in batch vs. non-batch
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2021-07-20 01:47:46 -04:00 |
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Ross Thompson
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ae2371f2ce
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Added performance counters for dcache access and dcache miss.
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2021-07-19 22:12:20 -05:00 |
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David Harris
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678f705415
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 18:19:59 -04:00 |
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Kip Macsai-Goren
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3a73ae0a8b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 16:46:46 -04:00 |
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bbracker
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78e513160e
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put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
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2021-07-19 16:19:24 -04:00 |
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bbracker
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76be84fa92
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whoops MTIMECMP is always 64 bits
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2021-07-19 15:40:53 -04:00 |
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bbracker
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fb6e618b1c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 15:13:14 -04:00 |
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bbracker
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77b690faf0
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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Kip Macsai-Goren
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c1c564d54c
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added changes to priority encoders from synthesis branch (correctly this time I hope)
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2021-07-19 15:06:14 -04:00 |
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Ross Thompson
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5edd513f8c
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Furture simplification of the dcache ReadDataW update.
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2021-07-19 12:46:31 -05:00 |
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Ross Thompson
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2ee97efb9c
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Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
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2021-07-19 12:32:16 -05:00 |
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bbracker
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986b7a8252
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change sram1rw to have a small delay so that we don't have signals changing on clock edges
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2021-07-19 11:30:07 -04:00 |
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David Harris
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1b55f584c7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 10:34:18 -04:00 |
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James Stine
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62b4ef6953
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delete sbtm_a4 and sbtm_a5 as they are not needed
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2021-07-19 08:06:00 -05:00 |
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James Stine
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892bc68918
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remove sbtm3.sv - not needed
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2021-07-19 08:00:53 -05:00 |
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James Stine
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55f2720f89
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update part I on sbtm change
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2021-07-19 07:59:27 -05:00 |
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David Harris
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0c41b8102d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-19 00:25:06 -04:00 |
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Katherine Parry
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8d101548f1
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FDIV and FSQRT passes when simulating in modelsim
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2021-07-18 23:00:04 -04:00 |
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David Harris
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4729a72167
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Updated FMA1 with parameterized size
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2021-07-18 20:40:49 -04:00 |
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David Harris
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398e9583e9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-18 17:36:29 -04:00 |
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David Harris
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f22b6e7397
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Added FLEN, NE, NF to config and started using these in FMA1
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2021-07-18 17:28:25 -04:00 |
|
Katherine Parry
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3527620c0b
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fdivsqrt inegrated, but not completley working
|
2021-07-18 14:03:37 -04:00 |
|
David Harris
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e31d2ef9f5
|
Renamed pagetablewalker to hptw
|
2021-07-18 04:11:33 -04:00 |
|
David Harris
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e962324d00
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LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
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2021-07-18 03:51:30 -04:00 |
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David Harris
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40c5d3ced7
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HPTW: Simpliifieid PRegEn
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2021-07-18 03:35:38 -04:00 |
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David Harris
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a5a7be3e03
|
Removed EndWalk signal and simplified TLBMissReg
|
2021-07-18 03:26:43 -04:00 |
|
Ross Thompson
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d0ed6e250a
|
Fixed LRSC in 64bit version. 32bit version is broken.
|
2021-07-17 20:58:49 -05:00 |
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David Harris
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3be88117c5
|
added lrsc.sv
|
2021-07-17 21:15:08 -04:00 |
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David Harris
|
c29a2ff8df
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
David Harris
|
3783b5dc00
|
moved subwordread to lsu
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2021-07-17 20:37:20 -04:00 |
|
David Harris
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84f579038c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-17 20:01:23 -04:00 |
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David Harris
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d441d4270c
|
LSU cleanup
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2021-07-17 20:01:03 -04:00 |
|
David Harris
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f21582906f
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Pushing HPTWPAdrM flop into LSUArb
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2021-07-17 19:39:18 -04:00 |
|
David Harris
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989bb7c01b
|
Simplified VPN case statement
|
2021-07-17 19:34:01 -04:00 |
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Ross Thompson
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379cf6c188
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-17 18:27:44 -05:00 |
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David Harris
|
25450bd7c1
|
Finished HPTW TranslationPAdr simlification
|
2021-07-17 19:27:24 -04:00 |
|
Ross Thompson
|
053e9593af
|
Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before.
|
2021-07-17 18:26:29 -05:00 |
|
David Harris
|
217bf37668
|
Further TranslationVAdr simplification
|
2021-07-17 19:24:37 -04:00 |
|
David Harris
|
d8397b5e8b
|
Continued Translation Address Cleanup of TranslationPAdrMux
|
2021-07-17 19:16:56 -04:00 |
|
David Harris
|
6f73844427
|
Continued Translation Address Cleanup
|
2021-07-17 19:09:13 -04:00 |
|
David Harris
|
2e2e948023
|
Refining address interface between HPTW and LSU
|
2021-07-17 19:02:18 -04:00 |
|
David Harris
|
12cfe91362
|
Fixed bad register in I-FSD-01 Imperas test.
|
2021-07-17 17:08:07 -04:00 |
|
David Harris
|
e3bf8db80b
|
trap.sv comment cleanup
|
2021-07-17 16:01:07 -04:00 |
|
David Harris
|
b2c2194478
|
trap.sv cleanup
|
2021-07-17 15:57:10 -04:00 |
|
David Harris
|
777e983c19
|
Finished removing PageTableEntry redundant signals from hptw
|
2021-07-17 15:50:52 -04:00 |
|
David Harris
|
348e69c096
|
hptw: Removed NonBusTrapM from LSU
|
2021-07-17 15:24:26 -04:00 |
|
David Harris
|
49ec45d04d
|
hptw: Removed NonBusTrapM from LSU
|
2021-07-17 15:22:24 -04:00 |
|
David Harris
|
e55546da34
|
hptw: Propagating PageTableEntryF removal through IFU
|
2021-07-17 15:04:39 -04:00 |
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