David Harris
6b9cfe90d8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
bbracker
83a1f29c37
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
91a13999a9
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
Kip Macsai-Goren
fcb9b1f0e1
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
David Harris
cfe5c27946
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
a61411995a
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
06cf3a8403
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
Ross Thompson
9a49cf74c3
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
0a20e33971
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Ross Thompson
c4f7c65210
updated the branch predictor config.
2021-03-23 13:54:59 -05:00
Ross Thompson
cebb2bc44d
Temporary exe2memfile0.pl script to support starting addresses of 0.
2021-03-23 13:54:59 -05:00
