10 Commits

Author	SHA1	Message	Date
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
Ross Thompson	3cd8404917	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	11e5aad38a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	308cc34d6f	Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.	2022-02-04 23:49:07 -06:00
Ross Thompson	f6f0539e10	Got separate module for the sub cache line read.	2022-02-04 20:23:09 -06:00