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137 Commits

Author SHA1 Message Date
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
e0a30ecc22
Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
harshini
17724f7832 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
a53cdbd166
Update spill.sv 
Program clean up
 2023-06-12 12:50:11 -07:00
Harshini Srinath
7fa3b87275
Update irom.sv 
Program clean up
 2023-06-12 12:44:09 -07:00
Harshini Srinath
128e88a7a0
Update ifu.sv 
Program clean up
 2023-06-12 12:38:52 -07:00
Harshini Srinath
e2a9e257c7
Update decompress.sv 
Program clean up
 2023-06-12 12:27:55 -07:00
Harshini Srinath
a849fa78cb
Update CodeAligner.py 
Program clean up
 2023-06-12 12:25:47 -07:00
David Harris
e2e6f6f255 Added named support for Zicntr and Zihpm 2023-06-09 09:35:51 -07:00
Ross Thompson
e56497101a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
903f2f9063 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
340aac0934 Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check. 2023-05-26 16:00:14 -05:00
Ross Thompson
febb2442db Partial parameterization into mmu. 2023-05-24 16:12:41 -05:00
Ross Thompson
e33db7f9a7 More parameterization. Copied Lim. Still no slow down. 2023-05-24 14:49:22 -05:00
Ross Thompson
d3123fc00a Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
3de3a42f97 Merged changes. 2023-05-24 13:15:52 -05:00
Ross Thompson
b28a75f32a Updated headers to local branch history predictors. 2023-05-24 12:52:42 -05:00
Ross Thompson
6163fc29e1 Adds local history predictor. 
Fixes performance counters, but not coremark.
 2023-05-23 18:53:46 -05:00
Ross Thompson
03823a9bc1 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
e34b25511a Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
faf71294d6 Fixed bug in local history predictor. 2023-05-04 16:54:41 -05:00
Ross Thompson
e11d42b270 Almost working ahead pipelined local history predictor. 2023-05-04 16:17:31 -05:00
Ross Thompson
8da2b18543 Maybe I finally have the ahead pipelined local history predictor working. 2023-05-04 14:11:34 -05:00
Ross Thompson
afafa9718d Ahead pipelining is not yet working. :( 2023-05-03 17:41:38 -05:00
Ross Thompson
35a59a1193 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
c4d6724867 Updated configs for local branch history `defines. 2023-05-02 11:11:04 -05:00
Ross Thompson
9ee6ba8964 Added comment explaining the difference between global history and local history basic implementations. 2023-05-02 11:01:46 -05:00
Ross Thompson
799c25cc60 Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Ross Thompson
b9abb2a491 Maybe have the baseline local history predictor working. 2023-05-01 15:45:27 -05:00
Ross Thompson
89a242d143 Might actually have a correct implementation of local history branch prediction. 2023-04-24 13:05:28 -05:00
Ross Thompson
7588de5a36 Fixed the local branch predictor so that it at least compiles. 2023-04-24 11:06:53 -05:00
Limnanthes Serafini
95223bf11c More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
Sydney Riley
440e41bb3e expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Ross Thompson
69f6b291c6 Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
Ross Thompson
a27051b8a8 Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
ede9d49ce4 Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
e233b63752 Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Ross Thompson
4b539de184 Renamed signals to be consistent with textbook. 2023-03-06 18:29:31 -06:00