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Author	SHA1	Message	Date
David Harris	0a39f40d49	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-17 13:28:07 -08:00
David Harris	d026b0e2bf	Initial version of embench_arch_sweep.py	2023-11-17 13:27:57 -08:00
David Harris	27e9ef1cac	Merge pull request #484 from ross144/main ... Changed bpred-sim.py to only simulate 12 jobs at once.	2023-11-17 13:26:24 -08:00
Rose Thompson	8ddfdd44f6	bpred-sim only simulates 12 jobs at once.	2023-11-17 15:21:58 -06:00
David Harris	9d26fc9689	Merge pull request #483 from ross144/main ... Fixed branch predictor embench generation results	2023-11-17 10:07:30 -08:00
Rose Thompson	889d685524	Fixed bugs in paraseHPMC.py	2023-11-17 12:05:22 -06:00
Rose Thompson	556fe16b0a	Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.	2023-11-17 11:21:25 -06:00
Jacob Pease	93d217a40d	ahbsdc submodule actually added this time.	2023-11-16 17:46:48 -06:00
Jacob Pease	0aecc1ab75	Deleted vivado-risc-v directory and added ahbsdc.	2023-11-16 15:13:12 -06:00
Jacob Pease	e907cec4d3	Merge branch 'main' of github.com:jacobpease/cvw	2023-11-16 14:04:11 -06:00
Jacob Pease	402045b756	Replaced vivado-risc-v addins directory with new SDC repo.	2023-11-16 13:59:12 -06:00
Rose Thompson	b2184c6ac0	Removed the size opt tests from the branch predictor analysis.	2023-11-15 22:35:33 -06:00
David Harris	60be373cc2	Merge pull request #481 from ross144/main ... Fixed the BTB logger so sim_bp correctly reports BTB performance	2023-11-15 17:45:38 -08:00
Rose Thompson	c6a24240f3	Updates to btb logger processing.	2023-11-15 16:53:44 -06:00
Rose Thompson	c2dc92b109	Added btb reference data.	2023-11-15 16:39:35 -06:00
Rose Thompson	809ac2203d	Extended SeparateBranch to support both just branches and all control flow instructions.	2023-11-15 16:36:49 -06:00
Rose Thompson	7df5d34bf4	Fixed second bug in the logger script when branch logging enabled but counter logger not.	2023-11-15 14:56:02 -06:00
Rose Thompson	15eddc8069	Fixed bug in the btb branch logging. ... We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.	2023-11-15 14:51:47 -06:00
David Harris	b289e5275a	changed to head of riscv-arch-test	2023-11-15 09:48:13 -08:00
Rose Thompson	7aca4f0f97	Merge pull request #479 from davidharrishmc/main ... Removed and added back in riscv-arch-test to try to fix corruption	2023-11-15 08:46:42 -08:00
Rose Thompson	4551bf9e6f	Merge pull request #478 from davidharrishmc/dev ... Removed non-functioning Zfh from rv64gc	2023-11-15 08:46:24 -08:00
David Harris	5b4b04d763	Fixed typo in lsu parameter	2023-11-15 08:30:48 -08:00
David Harris	11b30292b9	Adjusted LSU misaligned buffer to fix synthesis warning	2023-11-15 08:19:50 -08:00
David Harris	c63cc95663	Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter	2023-11-15 08:15:01 -08:00
David Harris	2e3a1832f5	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-15 08:06:35 -08:00
David Harris	981df2fbd8	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
James E. Stine	43ff20d2f2	missing synth.tcl added for use with wrapper	2023-11-15 08:48:07 -06:00
James E. Stine	b654e47d70	Add wrapper passing automatically for individual designs vs. Wally	2023-11-15 08:45:25 -06:00
David Harris	e9f8203c58	Added back in riscv-arch-test	2023-11-15 06:07:57 -08:00
David Harris	68e108a2df	Removed riscv-arch-test submodule that was corrupted	2023-11-15 06:05:55 -08:00
David Harris	07b4f40b74	Added back riscv-arch-test fresh	2023-11-15 05:48:33 -08:00
David Harris	62b01b70db	Removed riscv-arch-test submodule that appears corrupted	2023-11-15 05:46:38 -08:00
David Harris	28cba247bf	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-14 19:14:03 -08:00
David Harris	8ca721f95e	Merge pull request #476 from naichewa/main ... Final SPI code review	2023-11-14 19:10:00 -08:00
David Harris	5b8806ffe5	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-14 15:19:22 -08:00
David Harris	db16833ee8	Restored Zfh to 0 for rv64gc because it breaks floating-point tests	2023-11-14 15:18:16 -08:00
naichewa	3dfaf08363	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
naichewa	7ecf35bc68	Final Code Review	2023-11-14 13:44:59 -08:00
Rose Thompson	c285177507	Patched up linux imperas testbench.	2023-11-14 14:20:13 -06:00
Rose Thompson	730d8e8e97	Merge pull request #474 from davidharrishmc/dev ... FP and synthesis cleanup	2023-11-14 12:03:01 -08:00
Rose Thompson	94d4de5498	Merge branch 'main' of github.com:ross144/cvw	2023-11-14 13:54:48 -06:00
Rose Thompson	9d55f5092b	Modified the device trees to include all the minor extensions.	2023-11-14 13:54:16 -06:00
David Harris	19e30ee89f	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
Rose Thompson	0120bb8376	Fixed the imperas testbench to be compatible with the config changes.	2023-11-14 12:57:44 -06:00
David Harris	efd9e35da8	Merge pull request #473 from ross144/main ... Missed a few files in the last pull request. Removes the fpga config from the linter.	2023-11-14 10:15:31 -08:00
Rose Thompson	33b123aa25	Added cbop to to rv32gc.	2023-11-14 10:55:22 -06:00
David Harris	1fe4b18057	Merge pull request #472 from ross144/main ... Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building	2023-11-14 08:34:06 -08:00
David Harris	78be798336	Merge pull request #471 from stineje/main ... Fix multitude of issues with plotPPA as well as issue related to Popen issuing too many synthesis	2023-11-14 05:51:20 -08:00
James E. Stine	22b9fee1c7	minor typo on ppaSynth and ppaAnalyze	2023-11-14 02:41:44 -06:00
James E. Stine	d20a798f79	fix plotPPA and other excruciatingly painful problems related to using allWidths and causing empty arrays to be used. This generates the normalized/unnormalized plots	2023-11-14 01:06:14 -06:00