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Author	SHA1	Message	Date
Rose Thompson	33b123aa25	Added cbop to to rv32gc.	2023-11-14 10:55:22 -06:00
David Harris	1fe4b18057	Merge pull request #472 from ross144/main ... Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building	2023-11-14 08:34:06 -08:00
David Harris	78be798336	Merge pull request #471 from stineje/main ... Fix multitude of issues with plotPPA as well as issue related to Popen issuing too many synthesis	2023-11-14 05:51:20 -08:00
James E. Stine	22b9fee1c7	minor typo on ppaSynth and ppaAnalyze	2023-11-14 02:41:44 -06:00
James E. Stine	d20a798f79	fix plotPPA and other excruciatingly painful problems related to using allWidths and causing empty arrays to be used. This generates the normalized/unnormalized plots	2023-11-14 01:06:14 -06:00
James E. Stine	7c8eff3af7	Modify ppaSynth.py to be able to not issue excess number of operations with Pool command. This is due to the original command using the Popen command, whereas, using the subprocess.call command solves this issue. The relieves the python script from issuing a ton of synthesis commands and using up all the licenses	2023-11-14 01:04:37 -06:00
Rose Thompson	508c0cb188	Fixed another bug in the updated script changes.	2023-11-13 18:12:02 -06:00
Rose Thompson	a5303d25aa	Merge branch 'main' of github.com:ross144/cvw	2023-11-13 18:10:35 -06:00
Rose Thompson	04cda8cb71	Fixed bugs in the updated fpga synthe script.	2023-11-13 18:10:22 -06:00
Rose Thompson	4302c0a3b0	Removed fpga config. No longer needed.	2023-11-13 17:50:29 -06:00
Rose Thompson	7f2d03df7f	Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.	2023-11-13 17:48:28 -06:00
Rose Thompson	b81bd35724	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	e7cf9de469	Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.	2023-11-13 16:44:02 -06:00
Rose Thompson	ed7829dba8	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
Rose Thompson	3a495f2552	Cleanup and optimization of Zicclsm.	2023-11-13 14:28:22 -06:00
Rose Thompson	a53b9403e2	Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.	2023-11-13 14:12:27 -06:00
Rose Thompson	17768471f8	Cleanup. ... Linux makefile wally tracer. probably reduce some complexity here.	2023-11-13 14:04:43 -06:00
Rose Thompson	2f7479966b	Merge branch 'Zicclsm'	2023-11-13 13:53:42 -06:00
Rose Thompson	b813fe8061	Updates to linux config files for sdc.	2023-11-13 13:53:23 -06:00
David Harris	2d1cf1bbd7	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-13 11:25:46 -08:00
David Harris	ddb8e75f9f	Merge pull request #470 from stineje/main ... Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector	2023-11-13 11:25:38 -08:00
Rose Thompson	7ff89380e0	Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.	2023-11-13 12:36:32 -06:00
Rose Thompson	8860aa9af5	Cleanup.	2023-11-13 12:35:11 -06:00
James E. Stine	cb0add51f4	Remove ppa_ prefix and modify ppaAnalyze.py to handle correct vector	2023-11-13 10:02:10 -06:00
David Harris	2180df4477	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
David Harris	0647142ffa	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-13 05:34:14 -08:00
David Harris	a570199ad5	Merge pull request #469 from stineje/main ... update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 05:33:37 -08:00
James E. Stine	964b5f9c50	update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 02:39:25 -06:00
David Harris	5e14f7c422	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-12 20:24:25 -08:00
David Harris	ee4f752d3c	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:27 -08:00
David Harris	24942f9054	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:14 -08:00
Rose Thompson	40e69b82da	Merge pull request #468 from davidharrishmc/dev ... Divider optimization	2023-11-12 20:05:44 -08:00
David Harris	75216f8b2a	Divider cleanup	2023-11-12 19:41:12 -08:00
David Harris	b49330c556	Explained sqrt preshifting	2023-11-12 10:05:54 -08:00
David Harris	fdda3d6cde	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
David Harris	65c5ec6e9d	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
Rose Thompson	b0dcfddfb1	Merge pull request #467 from davidharrishmc/main ... Sanity in FDIVSQRT bit counts	2023-11-11 16:37:25 -08:00
David Harris	ac1051f67b	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
David Harris	051286e703	Bug fixes related to size of fpdivsqrt bit count and number of cycles	2023-11-11 05:58:53 -08:00
David Harris	a3ca197a70	Fixed testbench-fp to reflect signal name changes	2023-11-11 04:05:34 -08:00
Rose Thompson	ec9fbee7db	Merge pull request #466 from stineje/main ... Add pap runs for sweep	2023-11-10 22:25:55 -08:00
Rose Thompson	bbfc8ad4a3	Merge pull request #465 from davidharrishmc/dev ... fdivsqrt cleanup	2023-11-10 22:25:09 -08:00
James E. Stine	4a6b2b0299	Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH	2023-11-10 21:10:35 -06:00
James E. Stine	1af093b368	Update ppa/ppaSynth.py for sky130 and better sweep parameterization	2023-11-10 21:07:36 -06:00
James E. Stine	48c1e19247	Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made	2023-11-10 21:06:24 -06:00
James E. Stine	26db31cfde	update README for ppaSynth.py	2023-11-10 21:05:42 -06:00
David Harris	35efb7082c	fdivsqrt parameter cleanup	2023-11-10 18:33:08 -08:00
David Harris	6ed5ba4a85	Simplified out LOGRK parameter	2023-11-10 18:19:41 -08:00
David Harris	1302a89baf	divider cleanup	2023-11-10 18:01:13 -08:00
David Harris	d92f3e0216	fdivsqrt cleanup	2023-11-10 16:42:32 -08:00