32 Commits

Author	SHA1	Message	Date
bbracker	23f479d225	remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR	2021-06-20 22:38:25 -04:00
Katherine Parry	2b67f25683	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
David Harris	35c74348a4	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
David Harris	679e507cc6	Added SUPPORTED to each peripheral in each config file	2021-06-17 21:36:32 -04:00
Katherine Parry	4177f4f148	Updated FMA	2021-06-14 13:42:53 -04:00
David Harris	0ffbd03139	More verilator fixes, but bpred is broken	2021-06-09 21:03:03 -04:00
Kip Macsai-Goren	a95a7a7b82	working version with new mmu comments, old boottim values	2021-06-08 15:20:25 -04:00
David Harris	b613f46c2d	Resized BOOT TIM to 1 KB	2021-06-08 14:04:32 -04:00
David Harris	2ae5ca19b5	Continued merge	2021-06-07 12:49:47 -04:00
David Harris	ff62000e2c	Second attept to commit refactoring config files	2021-06-07 12:37:46 -04:00
David Harris	dc0b19dfaa	Merge difficulties	2021-06-07 09:50:23 -04:00
David Harris	d5ec797ba4	Refactored configuration files and renamed testbench-busybear to testbench-linux	2021-06-07 09:46:52 -04:00
Kip Macsai-Goren	22e8e06ac7	moved privilege dfinitions into wally-constants, upgraded relevant includes	2021-06-04 17:55:07 -04:00
David Harris	a26bf37be8	Started MMU	2021-06-04 11:59:14 -04:00
James E. Stine	c89d3e01bb	Update to rv64icfd wally-config to run through FP tests	2021-05-21 09:22:17 -05:00
James E. Stine	44dc665fc5	Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)	2021-05-18 13:48:44 -05:00
Ross Thompson	72363f5c66	Added the ability to exclude branch predictor.	2021-04-26 14:27:42 -05:00
Noah Boorstin	6954e6df4c	buildroot: sim is now running! ... yes it only gets through 5 instructions right now. Yes that's my fault.	2021-04-17 14:44:32 -04:00
Domenico Ottolia	92bb38fa8c	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
Shreya Sanghai	0369fc5d1e	Cherry Pick merge of Shreya's localhistory predictor changes into main. ... fixed minor bugs in localHistory	2021-04-15 09:04:36 -05:00
Thomas Fleming	7126ab7864	Complete basic page table walker	2021-03-30 22:19:27 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	1091dd10c1	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Noah Boorstin	bc1a0c6ee7	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	a2b0af460e	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	36f0631203	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	9eed875886	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	74f1641c5a	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	4c8952de6a	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Shreya Sanghai	f0ec365117	added performance counters	2021-03-04 11:42:52 -05:00
Brett Mathis	79cb7ed571	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00