18 Commits

Author	SHA1	Message	Date
David Harris	316690c929	mmu cleanup	2023-01-14 18:14:38 -08:00
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
Ross Thompson	122c88ee46	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
Ross Thompson	5e63af5887	Reordered the adrdecs.	2022-08-28 13:38:57 -05:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	37f0b52520	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
David Harris	2b241f8bbd	Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding	2022-08-26 21:18:18 -07:00
David Harris	f0b4f69b65	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	20ba6fd19c	Reversed order of supported sized in adrdecs.	2022-08-23 11:14:53 -05:00
Ross Thompson	3b07584403	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
Ross Thompson	dc48d84dd6	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
David Harris	f0a7ae2bba	adrdecs comments	2022-02-28 20:33:41 +00:00
David Harris	e108eb5195	Modified address decoder for native access to CLINT	2022-02-28 19:13:14 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00