Katherine Parry
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8150305919
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-30 09:56:35 -06:00 |
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David Harris
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18f19ce44d
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fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression
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2022-12-30 06:40:25 -08:00 |
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Katherine Parry
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e5a76817df
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minor optimizations and renaming
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2022-12-29 15:54:17 -06:00 |
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Katherine Parry
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b469831b53
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one bitt removed from inital lignment shift
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2022-12-28 17:46:53 -06:00 |
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Cedar Turek
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6d933a88c7
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idiv passing radix 2, four copies
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2022-12-27 22:10:48 -08:00 |
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David Harris
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0a0ca0ae07
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cleanup
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2022-12-27 21:29:36 -08:00 |
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David Harris
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d6aad0f3c3
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Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
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2022-12-27 21:24:38 -08:00 |
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David Harris
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71f214df20
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Moved fdivsqrtexpcalc to its own file
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2022-12-26 08:45:43 -08:00 |
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David Harris
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0a067d342f
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Restored missing floating point load/store tests
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2022-12-25 22:28:14 -08:00 |
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Katherine Parry
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66510f38af
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reworked negitive sticky bit handeling in fma
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2022-12-23 17:01:34 -06:00 |
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Ross Thompson
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b6b30533e8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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942acb354e
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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David Harris
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a5dc09c97f
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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a6ffb4cef3
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Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
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2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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7a352edf13
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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9d1cb9337e
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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3bef12b108
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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cturek
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930fcbe956
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Kip Macsai-Goren
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055ca9ee37
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6662933c4
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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4e2f4855e6
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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350fdd944d
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Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit fb221d7b64.
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2022-12-04 00:01:58 +00:00 |
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cturek
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fb221d7b64
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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David Harris
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db5f3c15a4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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6079a01bc8
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update test list
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2022-12-02 04:28:47 -08:00 |
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David Harris
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0d23ab3ec1
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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David Harris
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3a8602523e
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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2f582cd91f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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10c2d45888
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Kip Macsai-Goren
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44ea8d8b22
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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cturek
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78c2ce5649
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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cturek
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9d30a832c3
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Reoredered tests for arch32m
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2022-11-09 18:42:00 +00:00 |
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cturek
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2cbe2fd70b
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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David Harris
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53a88fec8f
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Reorder embench tests to prevent crash
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2022-11-04 15:21:51 -07:00 |
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Ross Thompson
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a59df0c77d
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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David Harris
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e49e99548a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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030fb79a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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cb4c3ff1ce
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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ac864a6ca3
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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David Harris
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87cde2c427
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make QmM size b+1 indpenedent of radix
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2022-09-20 03:25:09 -07:00 |
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David Harris
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8e90862dad
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Removed EarlyTermShift from fdiv
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2022-09-19 08:44:23 -07:00 |
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David Harris
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498c053aab
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FP testbench
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2022-09-18 21:27:21 -07:00 |
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