Marcus Mellor
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fd08ff2e60
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-31 10:29:10 -05:00 |
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Mike Thompson
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9abfef7c39
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Merge pull request #179 from davidharrishmc/dev
Fixed broken regression: privileged tests and build root
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2023-03-31 10:56:27 -04:00 |
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Marcus Mellor
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219176db9b
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-31 09:54:02 -05:00 |
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Marcus Mellor
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09b2cd304f
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Address comments in openhwgroup/cvw#180
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2023-03-31 09:51:33 -05:00 |
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David Harris
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beb73f3ec2
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Merge pull request #182 from dherreravicioso/main
Added test cases to write to CSRs
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2023-03-31 06:32:12 -07:00 |
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Diego Herrera Vicioso
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e711948369
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Merge branch 'openhwgroup:main' into main
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2023-03-31 00:35:02 -07:00 |
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Diego Herrera Vicioso
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2d1806c5d0
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Merge pull request #1 from dherreravicioso/AW_DH_privunit
Added test coverage cases for writing to CSRs
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2023-03-31 00:34:21 -07:00 |
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David Harris
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4069f4ba8d
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Merge pull request #181 from kipmacsaigoren/bitmanip_cleanup
Bitmanip cleanup
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2023-03-30 19:23:54 -07:00 |
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Kevin Kim
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2c6359b097
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only pass in relevant comparator flag to ALU
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2023-03-30 19:15:33 -07:00 |
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Kevin Kim
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1e88ec7eac
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Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup
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2023-03-30 19:04:41 -07:00 |
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Kevin Kim
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27a5c9c5d6
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Merge branch 'openhwgroup:main' into bitmanip_cleanup
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2023-03-30 19:04:36 -07:00 |
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Marcus Mellor
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d4cb1a8582
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Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered
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2023-03-30 20:01:11 -05:00 |
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Marcus Mellor
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3afd963a9e
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Disable coverage for branches tested in fpu.s
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2023-03-30 19:44:55 -05:00 |
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David Harris
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da53f240d3
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Refactored InstrValidNotFlushed into CSR Write signals
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2023-03-30 17:06:09 -07:00 |
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David Harris
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406bb22b6a
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Started factoring out InstrValidNotFlushed from CSRs
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2023-03-30 14:56:19 -07:00 |
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David Harris
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f34218666a
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fctrl updated and buildroot working again
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2023-03-30 13:17:15 -07:00 |
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David Harris
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9129c3ac22
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fctrl continued cleanup
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2023-03-30 13:07:39 -07:00 |
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David Harris
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01c5d58a64
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fctrl continued cleanup
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2023-03-30 13:05:56 -07:00 |
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David Harris
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b2a102ce79
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Started to clean up fctrl
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2023-03-30 12:57:14 -07:00 |
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Alec Vercruysse
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4b58bb55f2
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Make entire cache write path conditional on READ_ONLY_CACHE
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2023-03-30 10:32:40 -07:00 |
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David Harris
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2924179424
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Merge pull request #176 from kipmacsaigoren/priv-tests
Fixed regression after cause CSR fix
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2023-03-30 07:02:47 -07:00 |
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Alessandro Maiuolo
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9b290669d5
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integrated tv generation for IFdivsqrt
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2023-03-29 20:57:26 -07:00 |
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Kip Macsai-Goren
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3805cf993a
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unnecessary comments cleanup
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2023-03-29 19:32:57 -07:00 |
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Kip Macsai-Goren
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cfb236dd13
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Merge branch 'priv-tests' of github.com:kipmacsaigoren/cvw into priv-tests
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2023-03-29 16:31:35 -07:00 |
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Kip Macsai-Goren
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a7c9d3d37b
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ported medelg fixes to 32 bit tests. Requires a make allclean
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2023-03-29 16:31:28 -07:00 |
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kipmacsaigoren
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5cc1bc97da
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Merge branch 'openhwgroup:main' into priv-tests
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2023-03-29 15:34:47 -07:00 |
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David Harris
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6934a32747
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Merge pull request #175 from SydRiley/main
Starting IFU coverage expansion
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2023-03-29 15:29:16 -07:00 |
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Sydney Riley
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4bd3121364
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Manual merge in the coverage64gc
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2023-03-29 15:25:27 -07:00 |
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Kip Macsai-Goren
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2e151b6b08
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updated tests to reflect non-writeable bits of deleg
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2023-03-29 15:24:00 -07:00 |
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Sydney Riley
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20fec0177d
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Corrected authorship for IFU.S tests file
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2023-03-29 15:20:46 -07:00 |
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Sydney Riley
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b0237eaa8b
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Starting IFU tests including c.fld compressed instruction
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2023-03-29 15:15:47 -07:00 |
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Kip Macsai-Goren
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491ef14b71
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Resolved ImperasDV receiving incorrect cause values
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2023-03-29 15:04:56 -07:00 |
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Noah Limpert
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6acf1dadda
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instantiate 5 4KiB arrays, aim to thrash all 4 ways
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2023-03-29 13:08:33 -07:00 |
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Noah Limpert
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1e07460d0e
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access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways
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2023-03-29 13:07:34 -07:00 |
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Alec Vercruysse
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d507f85190
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icache coverage improvements by simplifying logic
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2023-03-29 13:04:00 -07:00 |
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Ross Thompson
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5c4b753a1e
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Merge pull request #173 from davidharrishmc/dev
Test improvements including FPU coverage
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2023-03-29 13:00:25 -05:00 |
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David Harris
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9d8f9e4428
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Reduced number of bits in mcause and medeleg registers
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2023-03-29 07:02:09 -07:00 |
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David Harris
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59f825a54b
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-29 06:19:10 -07:00 |
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David Harris
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d604a4fd33
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Merge pull request #171 from AlecVercruysse/fix_152
add check for legal funct3 for IW instructions
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2023-03-29 06:18:31 -07:00 |
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David Harris
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d059da6eca
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Turned on FS bit in fpu.S coverage test
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2023-03-29 06:10:05 -07:00 |
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Limnanthes Serafini
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91fe85486c
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Log file cleanup
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2023-03-29 04:12:10 -07:00 |
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Limnanthes Serafini
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0ab06f08c4
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Log file cleanup
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2023-03-29 04:11:54 -07:00 |
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Limnanthes Serafini
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a4d4f0b914
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Log file cleanup
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2023-03-29 04:11:43 -07:00 |
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Limnanthes Serafini
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abf9da3c8b
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Git issues, repushing
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2023-03-29 04:10:47 -07:00 |
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Limnanthes Serafini
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7f2ce66a85
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A first pass at the Cache simulator.
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2023-03-29 04:03:55 -07:00 |
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Diego Herrera Vicioso
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36d7ddf501
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Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs.
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2023-03-28 22:48:17 -07:00 |
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David Harris
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115c042015
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Turned off hpm counters
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2023-03-28 21:28:56 -07:00 |
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David Harris
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f2c24b869d
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Simplified fctrl
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2023-03-28 21:13:48 -07:00 |
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David Harris
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3dc1c6673d
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Started adding fpu fctrl tests
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2023-03-28 21:13:25 -07:00 |
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Alec Vercruysse
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46df428e56
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add check for legal funct3 for IW instructions
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2023-03-28 15:59:48 -07:00 |
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