13 Commits

Author	SHA1	Message	Date
David Harris	1196e5c191	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
David Harris	f4957fdac1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
Kevin	b928d01bb8	dot stars conversions on the rest of the testbenches	2021-12-12 17:53:26 -08:00
Ross Thompson	74ffb48c0a	Mostly integrated FPGA flow into main branch. Not all tests passing yet.	2021-12-02 18:00:32 -06:00
Ross Thompson	d080041508	Removed unneeded check for icache ways.	2021-11-20 22:44:37 -06:00
David Harris	c306884e2c	Adding custom Wally test infrastructure	2021-11-01 08:48:46 -07:00
David Harris	717f9d48e9	tesgen cleanup, added riscv-arch-test D tests	2021-10-29 22:31:48 -07:00
David Harris	0421b7af56	Changes for floating point sims	2021-10-27 10:37:35 -07:00
David Harris	47124f36c8	Added synchronizer to reset	2021-10-25 10:05:41 -07:00
David Harris	8b1dc81d34	more lsu/ifu lint cleanup	2021-10-23 12:00:32 -07:00
David Harris	8b854bb1c2	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	3407b63c8a	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
David Harris	a077735ecc	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00