Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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David Harris
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3e8026dc21
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Configurable number of performance counters
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2021-06-10 09:41:26 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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James E. Stine
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44dc665fc5
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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Shreya Sanghai
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7e9a0602ea
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fixed bugs in global history to read latest GHRE
Cherry pick Shreya's commits into main branch.
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2021-04-15 08:55:22 -05:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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ushakya22
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6b9ae41302
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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