Github_Repos/cvw
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5,216 Commits 5 Branches 2 Tags 53 MiB
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2138 Commits

Author SHA1 Message Date
David Harris
ef83309ea9 Added missing PLIC_GPIO_ID to two config files 2023-01-27 15:23:32 -08:00
David Harris
d78f8d76cc Fixed license header for config files to SolderPad 2023-01-27 15:17:17 -08:00
Ross Thompson
6d75e3c22b Clarified gshare bp. 2023-01-27 16:40:20 -06:00
David Harris
3906e706fd Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
5a81a26c9e Removed int/integer from parameters) 2023-01-27 14:27:04 -08:00
Ross Thompson
857004c3a3 Removed pessimistic x propagation issue for wally32priv test in the branch predictor. 2023-01-27 15:28:31 -06:00
Ross Thompson
c1ae7c068e Found issue with branch predictor. 2023-01-27 13:13:55 -06:00
David Harris
4b196736a5 Renamed ram2p1rw1be to match modeule name 2023-01-27 09:54:50 -08:00
Ross Thompson
a212960352 Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. 2023-01-27 11:34:45 -06:00
David Harris
237e3a620f Removed suggestion about make allclean 2023-01-27 05:57:05 -08:00
David Harris
767cfdc8a5 Fixed typo in bpred preventing compiling 2023-01-27 05:55:53 -08:00
David Harris
c2139eba93 renamed brpred to bpred 2023-01-27 05:55:31 -08:00
David Harris
947713f1f3 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-26 14:52:25 -08:00
Ross Thompson
4fa2dcc2a5 Changed the performance counters to track different data. 
Now rather than tracking jump(r) we track jump(r) and taken branches.
 2023-01-26 13:21:28 -06:00
Ross Thompson
6025bbc9ae Fixed another bug with the compressed instruction class decode. 2023-01-26 12:19:33 -06:00
Ross Thompson
a8d5ba1ea4 Fixed compressed branch class decode. 2023-01-26 11:07:47 -06:00
Ross Thompson
3577220625 Improved no class prediction mode. 2023-01-26 10:54:43 -06:00
Ross Thompson
19a964325a Modified the RAS to correctly repair itself. 2023-01-25 23:33:03 -06:00
Ross Thompson
3dc441ff8c Intermediate commit. Passes regression tests, but RAS is not correct. 2023-01-25 19:39:18 -06:00
Ross Thompson
63617b56cf Fixed typos. 2023-01-25 18:51:09 -06:00
Ross Thompson
3b4d49a358 RAS is now compliant with our header and documentation guide. 2023-01-25 17:18:07 -06:00
Ross Thompson
5da1aeeef1 Improved RAS again. 2023-01-25 17:10:52 -06:00
Ross Thompson
2f0e40402b Improved RAS. 2023-01-25 17:06:25 -06:00
Ross Thompson
724ae13cc2 More branch predictor improvements. 2023-01-25 16:03:02 -06:00
Ross Thompson
fd1f7d4d34 Cleaned up branch predictor. 2023-01-25 15:29:55 -06:00
Ross Thompson
56a24d02e8 Fixed subtle bug in btb. 2023-01-25 15:16:53 -06:00
Ross Thompson
16142eca59 Added logic to forward btb prediction results. 2023-01-25 13:02:20 -06:00
Ross Thompson
4550966678 More btb cleanup. 2023-01-25 12:14:18 -06:00
Ross Thompson
40b4811d2b Found minor bug in gshare. 2023-01-25 12:08:54 -06:00
Ross Thompson
afdcfeb93b BTB cleanup. 2023-01-25 12:05:13 -06:00
Ross Thompson
7e1363bfad Optomized gshare. 2023-01-25 11:41:16 -06:00
Ross Thompson
b931110f2d Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
ad6f7041b4 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
56369f7641 Removed old versions of gshare. 2023-01-24 17:26:54 -06:00
Ross Thompson
1acbdaeca6 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
1170dc7250 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7d1109fc24 Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
2157970adf Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
David Harris
490ca23c87 Merge remote-tracking branch 'upstream/main' into dev 2023-01-24 09:40:07 -08:00
David Harris
f28b0e5c1a bpred input spacing cleanup 2023-01-24 06:14:31 -08:00
David Harris
5233117568 bpred tab cleanup 2023-01-24 05:42:34 -08:00
Ross Thompson
5494ee2159 Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
a4d5ccc4d6 Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
1439ff02c7 Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e9f435bbda Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
af6899472d Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
fc6cf1f198 formatting 2023-01-23 10:54:06 -08:00
David Harris
2d7f39672a Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
626bcd8608 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
45218863af test 2023-01-20 15:23:38 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
a968ae2f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
e87c2b2724 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
0123776037 Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
2e9b5f9ae4 Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
bcadbd7104 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
ecceea177a Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
3d202ed2fd Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
d3df8e062e Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
1ecf4e4cc9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
74ab386735 More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
26cb45e240 renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
29f45d6203 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
2cca457f14 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
da4eec7e0e Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
23ab178192 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
928e06d4fa Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
569a016efa Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
0488723db9 Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
9df5fdbd89 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
25b607566c RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
b027921902 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
ea96c2375f Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
e380fd71ff Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
d9d5b99218 update 2023-01-19 13:29:46 +00:00
Ross Thompson
47fdff6488 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
49daa736b1 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
cd2f7c6208 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
7289fa8d44 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
026d09b79b More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
19e4d0f7cd Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
997dda11a8 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
fb234d506d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
469efa61af Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cbf46f417a Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
22eee73a45 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
2048edb7a0 Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
40c0e67930 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
2622f5dfb8 Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
a6b14eb9ee Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
0b244e289c Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
affca27ec4 Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
58a07399a2 Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
fc5424fa62 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
607c64e0ee Formating. 2023-01-18 16:52:46 -06:00