Ross Thompson
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939095615f
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Fixed parameterization in testbench.
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2023-01-31 00:11:01 -06:00 |
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Ross Thompson
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8feac6d242
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Parameterized testbench branch predictor preload.
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2023-01-31 00:08:11 -06:00 |
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Ross Thompson
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a9a7054e2f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
This merges the branch predictor improvements into the main repo.
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2023-01-29 15:24:20 -06:00 |
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Ross Thompson
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74b4f78099
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Found bug in gshare.
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2023-01-29 15:03:25 -06:00 |
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Ross Thompson
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e1fd5925b0
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Fixed typo in testbench branch logger.
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2023-01-29 01:00:52 -06:00 |
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Ross Thompson
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f62fbedbe8
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Fixed another bug with the branch logger.
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2023-01-29 00:59:59 -06:00 |
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Ross Thompson
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8e73f6b467
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Fixed bug in the branch logger.
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2023-01-29 00:58:50 -06:00 |
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Ross Thompson
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65a31381da
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Updated testbench for branch logger.
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2023-01-29 00:56:11 -06:00 |
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David Harris
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94daedeed6
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Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED
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2023-01-28 18:52:00 -08:00 |
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David Harris
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e4e7e827d6
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Renamed BUS to BUS_SUPPORTED
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2023-01-28 18:35:53 -08:00 |
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David Harris
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a0b4e7fb24
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Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED
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2023-01-28 18:17:42 -08:00 |
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Ross Thompson
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6371d91b37
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Added another performance counter to track overall branch miss-predictions.
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2023-01-28 17:50:46 -06:00 |
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David Harris
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3906e706fd
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Removed integer from localparams
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2023-01-27 14:40:06 -08:00 |
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David Harris
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3d13683c07
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Continued framework for B instructions
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2023-01-20 14:27:13 -08:00 |
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Ross Thompson
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340e1797ea
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More cleanup and formatting.
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2023-01-20 12:09:21 -06:00 |
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Ross Thompson
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5b5a615e4a
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Integrated the missing zifence tests into the regression test.
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2023-01-20 10:34:49 -06:00 |
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Ross Thompson
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caff6e788c
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Somehow the imperas files spilled into the main branch.
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2023-01-17 15:39:34 -06:00 |
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Ross Thompson
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cf608ee45f
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Possible optimization of gshare.
I don't believe the Writeback stage ghr is needed.
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2023-01-13 12:39:29 -06:00 |
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Ross Thompson
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94f24d3f58
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Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
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Ross Thompson
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6a616617d1
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Restored to default configuration.
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2023-01-09 00:21:45 -06:00 |
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Ross Thompson
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bf08c57ab0
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Added branch outcome logger to testbench
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2023-01-07 13:16:57 -06:00 |
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Ross Thompson
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f119b492bb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-06 15:18:13 -06:00 |
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Ross Thompson
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7223d1e05c
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Added python script to post process performance counter metrics.
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2023-01-06 15:15:54 -06:00 |
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Ross Thompson
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09bb733088
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Added code to print out performance counters at end of each test.
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2023-01-05 18:00:11 -06:00 |
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Ross Thompson
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206bc7daa6
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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David Harris
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8bc753a291
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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3d95aa3423
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Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
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2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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376b01fcb8
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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ebdac1a9d0
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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2457448e29
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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Ross Thompson
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5e5cca6ae1
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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ac3e02692b
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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8692ccbafb
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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6581490f9c
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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David Harris
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921a49921b
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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906f6f2990
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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109bcd470e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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David Harris
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6222e15946
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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32f86b1b6b
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Still not working with rv32ic.
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2022-08-25 15:03:54 -05:00 |
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Ross Thompson
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4ad7ccc7f7
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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