Ross Thompson
ab509614bb
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
857f59ab5c
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
8a035104ac
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
James E. Stine
c89d3e01bb
Update to rv64icfd wally-config to run through FP tests
2021-05-21 09:22:17 -05:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
James E. Stine
44dc665fc5
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
2021-05-18 13:48:44 -05:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Elizabeth Hedenberg
170f072b52
pushing coremark to main branch
2021-05-11 21:33:39 -04:00
Shriya Nadgauda
c5a306426a
finishing merge conflict changes
2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6
merge conflict fixes
2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a
updated pipeline tests
2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg
2d1d929485
coremark print statment
2021-05-03 19:35:08 -04:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
bbracker
1fcd43e844
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Ross Thompson
818c0abc89
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Ross Thompson
72363f5c66
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
8e5409af66
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
a3487a9e47
do script refactor
2021-04-24 09:32:09 -04:00
bbracker
74b35ac57a
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Noah Boorstin
3f0ead9d4e
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
6954e6df4c
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
290b3424e5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
92bb38fa8c
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Shreya Sanghai
0369fc5d1e
Cherry Pick merge of Shreya's localhistory predictor changes into main.
...
fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
Shreya Sanghai
7e9a0602ea
fixed bugs in global history to read latest GHRE
...
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
c91436d3b7
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
bbracker
31c6b2d01f
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
350fe87119
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Shreya Sanghai
df149d1be7
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
Shreya Sanghai
b544526766
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Teo Ene
7c364a26e9
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
eca2427f94
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864
Complete basic page table walker
2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Teo Ene
385ce9a8f9
Added BPTYPE to coremark_bare config
2021-03-24 16:38:29 -05:00
Ross Thompson
6a050219d4
updated the branch predictor config.
2021-03-23 13:54:59 -05:00
Ross Thompson
2b0f7cdd42
Temporary exe2memfile0.pl script to support starting addresses of 0.
2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Noah Boorstin
77dd0b4504
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
bbracker
11d4a8ab34
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Shreya Sanghai
bbe0957df5
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
