161 Commits

Author	SHA1	Message	Date
Ross Thompson	fa0080ca70	Modified the mmu to not mux the lower 12 bits of the physical address and instead directly ... assign from the input non translated virtual address. Since the lower bits never change there is no reason to place these lower bits on a longer critical path. The cache and lsu were previously using the lower bits from the virtual address rather than the physical address. This change will allow us to keep the shorter critical path and reduce the complexity of the lsu, ifu, and cache drawings.	2022-01-06 23:19:09 -06:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
Ross Thompson	e74e8c2e86	Changed names of address in caches. ... Removed old cache files.	2022-01-05 22:19:36 -06:00
Ross Thompson	1ab3a17ff7	Updates to support fpga.	2022-01-05 18:07:23 -06:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
Ross Thompson	98be8201b2	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	fffaf654e6	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	13dbf3cc0f	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	d1a7416028	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00