Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
5,242 Commits 5 Branches 2 Tags 53 MiB
a8afdf1741
Commit Graph

20 Commits

Author SHA1 Message Date
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
ed54959378 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
1d7949513d More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
Ross Thompson
2e00186eea Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00