Alessandro Maiuolo
3990417d70
integrated tv generation for IFdivsqrt
2023-03-29 20:57:26 -07:00
Kip Macsai-Goren
94f03b0d78
unnecessary comments cleanup
2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
dded6a640e
Merge branch 'priv-tests' of github.com:kipmacsaigoren/cvw into priv-tests
2023-03-29 16:31:35 -07:00
Kip Macsai-Goren
7881c245a2
ported medelg fixes to 32 bit tests. Requires a make allclean
2023-03-29 16:31:28 -07:00
kipmacsaigoren
aec27965af
Merge branch 'openhwgroup:main' into priv-tests
2023-03-29 15:34:47 -07:00
David Harris
f5c66b4464
Merge pull request #175 from SydRiley/main
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Starting IFU coverage expansion
2023-03-29 15:29:16 -07:00
Sydney Riley
6c1f9de8c2
Manual merge in the coverage64gc
2023-03-29 15:25:27 -07:00
Kip Macsai-Goren
414cd26a9d
updated tests to reflect non-writeable bits of deleg
2023-03-29 15:24:00 -07:00
Sydney Riley
287df517b9
Corrected authorship for IFU.S tests file
2023-03-29 15:20:46 -07:00
Sydney Riley
ede13491ef
Starting IFU tests including c.fld compressed instruction
2023-03-29 15:15:47 -07:00
Kip Macsai-Goren
da905b4eb9
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
Noah Limpert
0fea40282a
instantiate 5 4KiB arrays, aim to thrash all 4 ways
2023-03-29 13:08:33 -07:00
Noah Limpert
0e08c4393d
access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways
2023-03-29 13:07:34 -07:00
Alec Vercruysse
dac011c1d2
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
289b1ac3f6
Merge pull request #173 from davidharrishmc/dev
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Test improvements including FPU coverage
2023-03-29 13:00:25 -05:00
David Harris
de2a0da9e9
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
David Harris
96e3c3bea8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-29 06:19:10 -07:00
David Harris
e858d8a2ff
Merge pull request #171 from AlecVercruysse/fix_152
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add check for legal funct3 for IW instructions
2023-03-29 06:18:31 -07:00
David Harris
0e02378532
Turned on FS bit in fpu.S coverage test
2023-03-29 06:10:05 -07:00
Limnanthes Serafini
cfb58a32b4
Log file cleanup
2023-03-29 04:12:10 -07:00
Limnanthes Serafini
959a96a9fe
Log file cleanup
2023-03-29 04:11:54 -07:00
Limnanthes Serafini
a9d59c2196
Log file cleanup
2023-03-29 04:11:43 -07:00
Limnanthes Serafini
0216b1d412
Git issues, repushing
2023-03-29 04:10:47 -07:00
Limnanthes Serafini
9049945b21
A first pass at the Cache simulator.
2023-03-29 04:03:55 -07:00
Diego Herrera Vicioso
4fa2959e56
Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs.
2023-03-28 22:48:17 -07:00
David Harris
4c41589329
Turned off hpm counters
2023-03-28 21:28:56 -07:00
David Harris
043e4fe5f4
Simplified fctrl
2023-03-28 21:13:48 -07:00
David Harris
7132271a83
Started adding fpu fctrl tests
2023-03-28 21:13:25 -07:00
Alec Vercruysse
bfb4f0d6eb
add check for legal funct3 for IW instructions
2023-03-28 15:59:48 -07:00
David Harris
77affa7ccd
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:33:18 -07:00
David Harris
cac9d31696
Merge pull request #170 from ross144/main
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Fixed issue 148 and problems with i/d cache address loggers.
2023-03-28 14:32:54 -07:00
Ross Thompson
73e6972f0b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
Ross Thompson
b4338a5a50
Modified the testbench to not use the loggers for unsupported configurations.
2023-03-28 16:27:54 -05:00
David Harris
5e352bf72e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
6b58cb8d65
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 16:22:26 -05:00
Ross Thompson
34dd2850e0
Disable loggers by default.
2023-03-28 16:20:45 -05:00
Ross Thompson
cef75cfe06
Now reports if there is a hit or miss.
2023-03-28 16:20:14 -05:00
Ross Thompson
a48049f6fe
Restored performance counter reports.
2023-03-28 16:15:05 -05:00
Ross Thompson
7cc8d4f20c
Now have logging of i/d cache addresses, but the performance counter reports are x's.
2023-03-28 16:09:54 -05:00
Ross Thompson
f2edf0ff86
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 14:47:16 -05:00
Ross Thompson
69f6b291c6
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
adabb7c236
comment formatting
2023-03-28 11:40:19 -07:00
Kevin Kim
4c9670a082
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-28 11:31:18 -07:00
David Harris
f0cab709f2
Added support (untested) for half and quad conversions
2023-03-28 10:53:06 -07:00
David Harris
40311c4f62
fixed fp->fp conversions
2023-03-28 10:35:41 -07:00
David Harris
e5955c5dd8
support more fp -> fp conversions
2023-03-28 10:28:01 -07:00
David Harris
fd2d08f501
Fixed fmv decoder
2023-03-28 10:21:33 -07:00
Ross Thompson
d55b0c8c1f
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
82ae3a74e2
Fixed bitrot in testfloat tests
2023-03-28 09:35:19 -07:00
David Harris
20d8c2476e
Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP
2023-03-28 09:08:48 -07:00
