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a54c231489
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655 Commits

Author SHA1 Message Date
Ross Thompson
a54c231489 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
Ross Thompson
c7b97d0339 Added back in function name to wave.do 2021-05-03 09:04:48 -05:00
Ross Thompson
c0a4b7cb17 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
David Harris
a37d9b5e8e Fixed lint error in div 2021-05-03 09:26:12 -04:00
Noah Boorstin
b32128465c busybear: remove now unneeded hack for fixed CSR issue 2021-05-01 15:17:04 -04:00
Katherine Parry
db95151d8d fpu imperas tests run 2021-05-01 02:18:01 +00:00
Noah Boorstin
48d32c1daf rollback regression to 400k instrs for busybear 2021-04-29 20:59:30 -04:00
Domenico Ottolia
d03ca20dc9 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Ross Thompson
818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Domenico Ottolia
c60c4f4adc Minor improvements to scause test 2021-04-29 16:48:07 -04:00
Domenico Ottolia
c8a81779ca Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Domenico Ottolia
6fc04768f5 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
7ae5d4d11e Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
9dfbfd5772 fix to pcm bug 2021-04-29 15:21:08 -04:00
ushakya22
77210527c1 Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
4fae8088e3 Add medeleg tests 2021-04-29 15:02:36 -04:00
Jarred Allen
bf54c9b0b2 Enhance lint-wally functionality 2021-04-29 14:48:41 -04:00
Jarred Allen
ebd9c0ee29 Remove signal which no longer exists from default waves, so sim-wally works 2021-04-29 14:41:10 -04:00
Jarred Allen
8fd9cc679b Fix compile error in branch predictor 2021-04-29 14:36:56 -04:00
Shreya Sanghai
1e57c6bb92 fixed bug in gshare, global and local history BP 2021-04-29 06:14:32 -04:00
Noah Boorstin
a4dad3403e same but do that right this time 2021-04-28 14:27:28 -04:00
Domenico Ottolia
60dc6aaf48 Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests 2021-04-27 21:47:38 -04:00
Noah Boorstin
44606b6c19 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
8ae28e7887 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
ff1a6b63ed ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Ross Thompson
afbb100860 Fixed issue with not saving the first cache block read on a miss spill. 2021-04-26 12:57:34 -05:00
Noah Boorstin
ee628e388a minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
Ross Thompson
467a463c13 Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests. 2021-04-26 10:44:27 -05:00
bbracker
31a0387136 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
86946266cf thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
c21bd8a463 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-23 20:12:27 -04:00
Thomas Fleming
e3672ca23f Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Thomas Fleming
288a6d82ce Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
David Harris
85eb6bcf1a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-23 19:04:29 -04:00
David Harris
9415e00bfa Fixed exe2memfile.pl to handle large files 2021-04-23 19:04:16 -04:00
Ross Thompson
27ef10df07 almost working icache. 2021-04-23 16:47:23 -05:00
Noah Boorstin
09755251bc busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
c66e63ff70 adding pipeline testing 2021-04-23 14:19:17 -04:00
Jarred Allen
c91f1e197b Remind people to run make allclean when a regression fails 2021-04-22 19:21:00 -04:00
Ross Thompson
020fb65adf Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
da76b80991 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00