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3,526 Commits 5 Branches 2 Tags 53 MiB
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Commit Graph

184 Commits

Author SHA1 Message Date
David Harris
c3bfa53db0 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
69243f41ad Fixed imperas C tests 2021-12-26 04:45:06 +00:00
Ross Thompson
db76878581 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
de8e2008d2 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
13b65fa785 increase niceness of automatic checkpoint generation 2021-11-20 12:48:23 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
24c5796680 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
e585a173e5 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
31d38286da make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
730c52da23 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
db268471b6 added some missing files 2021-11-01 13:36:07 -07:00
David Harris
0c829dd62c simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb rearranging testgen 2021-10-29 22:28:37 -07:00
David Harris
ca700610f8 removed referenc outputs 2021-10-26 08:51:49 -07:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
David Harris
0e4f6392d6 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00