Ross Thompson
69f6b291c6
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
730f3ac84e
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
c4c7f5378e
Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault
2023-03-22 06:29:30 -07:00
David Harris
77fb1b57f4
Fix Issue 145
2023-03-22 04:33:14 -07:00
Ross Thompson
a27051b8a8
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
ede9d49ce4
Changes BTA to BPBTA.
2023-03-12 14:36:46 -05:00
Ross Thompson
e233b63752
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
Ross Thompson
4b539de184
Renamed signals to be consistent with textbook.
2023-03-06 18:29:31 -06:00
Ross Thompson
6fc157e628
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
Ross Thompson
e831efddaf
Renamed InstrFirstHalf to InstrFirstHalfF.
2023-03-06 17:48:57 -06:00
Ross Thompson
7dd8fa16c1
Renamed BTB misprediction to BTA.
2023-03-03 00:18:34 -06:00
Ross Thompson
4b501f6e03
Added the i and d cache cycle counters.
2023-03-02 23:54:56 -06:00
Ross Thompson
3d1ffac7d7
Cleaned up branch predictor performance counters.
2023-03-01 17:05:42 -06:00
Ross Thompson
a61f8bc4cf
Set bp to use instruction class prediction by default.
2023-03-01 11:52:42 -06:00
Ross Thompson
e8744684cd
Branch predictor cleanup.
...
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
2023-03-01 11:24:24 -06:00
Ross Thompson
08a1153ae9
More btb cleanup.
2023-03-01 10:47:00 -06:00
Ross Thompson
dd2433f7ff
Minor fix to btb.
2023-03-01 10:45:40 -06:00
Ross Thompson
2773048bd4
Name cleanup.
2023-02-28 17:48:58 -06:00
Ross Thompson
87013ccaf0
Found the performance bug with the branch predictor btb power saving update.
2023-02-28 15:57:34 -06:00
Ross Thompson
8af61c0cc0
Name changes to reflect diagrams.
2023-02-28 15:37:25 -06:00
Ross Thompson
a823d8d021
Undid the btb update as it reduces performance.
2023-02-28 15:21:56 -06:00
Ross Thompson
3261f31e88
This icpred and btb changes are causing a performance issue.
2023-02-27 20:00:50 -06:00
Ross Thompson
69e8358639
Modified the BTB to save power by not updating when the prediction is unchanged.
2023-02-27 17:37:29 -06:00
Ross Thompson
44361f0a34
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-27 09:48:03 -06:00
Ross Thompson
a81cc883e9
Signal name changes.
2023-02-27 00:39:19 -06:00
Ross Thompson
447f6b1443
Branch predictor cleanup.
2023-02-26 21:28:36 -06:00
Ross Thompson
3804626166
Create module for instruction class prediction and decoding.
2023-02-26 20:20:30 -06:00
David Harris
d2fd34efe6
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
Ross Thompson
bb276da6eb
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-02-26 12:06:06 -06:00
David Harris
4579a9d0c2
Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
2023-02-26 09:38:32 -08:00
Ross Thompson
7500bb75c6
PHT was enabled using the wrong ~flush and ~stall.
2023-02-24 22:57:32 -06:00
Ross Thompson
63b9f9ca3d
gshare cleanup.
2023-02-24 22:55:51 -06:00
Ross Thompson
ed7ab402ad
More signal renames.
2023-02-24 19:56:55 -06:00
Ross Thompson
e549bec060
Renamed signals to match new figures.
2023-02-24 19:51:47 -06:00
Ross Thompson
6ff524d843
Renamed signals to match figure 10.18.
2023-02-24 19:22:14 -06:00
Ross Thompson
4058a49985
Possible fix to btb performance issue.
2023-02-24 18:36:41 -06:00
Ross Thompson
5c52827f51
Cleanup.
2023-02-24 18:20:42 -06:00
Ross Thompson
d030d323fd
Completed critical path gshare fix.
2023-02-24 18:02:00 -06:00
Ross Thompson
c2021927ce
Prep to fix gshare critical path.
2023-02-24 17:54:48 -06:00
Ross Thompson
4ffaa75c2a
Modified btb forwarding logic to reduce critical path.
2023-02-24 17:47:43 -06:00
Ross Thompson
6e8791a0a5
Major cleanup of bp.
2023-02-23 16:19:03 -06:00
Ross Thompson
d880720b7e
Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}.
2023-02-23 15:55:34 -06:00
Ross Thompson
500764f97b
Branch predictor cleanup.
2023-02-23 15:15:14 -06:00
Ross Thompson
70f7f59332
Moved more branch predictor logic into the performance counter block.
2023-02-23 15:14:56 -06:00
Ross Thompson
195343c84f
Added if generate around bp logic only used with performance counters.
2023-02-23 14:39:31 -06:00
Ross Thompson
ed91fc5ce3
Renamed PCPredX to BTAX.
2023-02-23 14:33:32 -06:00
Ross Thompson
1af7b8051e
Fixed bug in basic gshare.
2023-02-22 12:54:46 -06:00
Ross Thompson
fd5b940839
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-22 09:11:57 -06:00
Ross Thompson
5ecbc830cf
Oups. Turns out dc_shell does not like string parameters.
...
Switched gshare to use an integer parameter to select between gshare and global.
2023-02-22 09:11:46 -06:00
David Harris
bc4410e686
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-21 09:58:18 -08:00
