bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
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Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Thomas Fleming
6f23858609
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Thomas Fleming
f0c926cf68
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
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Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
89a2fe5741
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
bbracker
5327dcfcc8
instrfaults not respecting stalls bugfix
2021-03-25 00:16:26 -04:00
Ross Thompson
cdb7d15709
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Shreya Sanghai
09b90557f7
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
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Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Thomas Fleming
062c4d40da
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Shreya Sanghai
23a7c8cd92
made performance counters count branch misprediction
2021-03-16 11:24:17 -04:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
