22 Commits

Author	SHA1	Message	Date
Ross Thompson	918464c236	Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.	2023-06-05 15:42:05 -05:00
Ross Thompson	c7e515634d	I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.	2023-05-26 13:56:51 -05:00
Ross Thompson	8cf38b28aa	The privileged unit is parameterized using Lim's method.	2023-05-26 12:03:46 -05:00
Ross Thompson	625d365f3e	Fixes load and store stall counters.	2023-05-22 10:08:49 -05:00
Alexa Wright	fb517163f5	Excluded coverage for misaligned instructions	2023-04-10 23:18:25 -07:00
David Harris	9394389fec	Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed	2023-04-07 20:43:28 -07:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	6922298f21	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
Ross Thompson	0cb5369351	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	5b5677ccb8	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	aabb454d1c	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	cfca77172e	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	f32f8c109a	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	a313b10912	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	2dd693a3b3	Reordered performance counters and added space for new ones.	2023-03-02 23:04:31 -06:00
Ross Thompson	b98e007a53	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
Ross Thompson	a6917d07f3	Name cleanup.	2023-02-28 17:48:58 -06:00
Ross Thompson	2ebe600f54	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	8bd4a4c35b	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
Ross Thompson	fdd007a903	Found a bug where the d and i cache misses were not recorded in the performance counters.	2023-02-20 16:00:29 -06:00
David Harris	97ee3732fe	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-02-03 08:36:11 -08:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00