5 Commits

Author	SHA1	Message	Date
David Harris	72c1cc33f5	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
Ross Thompson	d430659983	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
David Harris	c117356432	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
David Harris	b2f7952b3d	Added cache configuration to config files	2021-07-19 18:19:46 -04:00
Katherine Parry	701ea38964	Fixed lint warning	2021-07-14 21:24:48 -04:00