15 Commits

Author	SHA1	Message	Date
Ross Thompson	eededd1ba9	Fixed remaining bugs in the imperas merge.	2023-01-31 13:04:26 -06:00
Ross Thompson	0678e70b4b	Merge branch 'imperas'	2023-01-31 12:46:22 -06:00
David Harris	b89fe9989e	Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED	2023-01-28 18:52:00 -08:00
David Harris	fa3643a064	Renamed BUS to BUS_SUPPORTED	2023-01-28 18:35:53 -08:00
David Harris	8a96dcf0ae	Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED	2023-01-28 18:17:42 -08:00
eroom1966	52ebac59b8	remove volatile for FFLAGS and FCSR	2023-01-18 13:33:57 +00:00
Ross Thompson	374f95ebf3	Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.	2023-01-17 18:24:46 -06:00
eroom1966	cf3223df22	refactor all rvvi into single initial block	2023-01-17 13:01:01 +00:00
eroom1966	2ead2cdaf4	Code refactor and addition of rvvi interface	2023-01-17 12:47:38 +00:00
Ross Thompson	14ecaabbf6	Nearly complete RVVI tracer. ... Missing PMP registers and performance counters other than MCYCLE and MINSTRET.	2023-01-12 18:43:39 -06:00
Ross Thompson	0ea0e7a9e1	rvvi trace is coming alone nicely.	2023-01-12 14:46:31 -06:00
Ross Thompson	9a180f88f7	Completely stripped down imperas simulation. ... run with vsim -c -do "do wally-pipelined-imperas.do rv64gc"	2023-01-12 12:48:38 -06:00
Ross Thompson	5112ffcbc9	Stripped out all signature checking. ... Removed multiple tests loop. Only runs 1 test now.	2023-01-12 12:45:44 -06:00
Ross Thompson	8ee80c5d54	Created separate imperas testbench. ... Resolved logger issue with the duplicated instructions after commit.	2023-01-12 12:07:07 -06:00
Ross Thompson	f59e1d03fc	Added instruction logger.	2023-01-12 10:09:34 -06:00