bbracker
4f50dd575d
buildroot added to regression because it passes regression
2021-06-18 09:49:30 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
5b96f7fbd7
making linux waveforms more useful
2021-06-17 08:37:37 -04:00
bbracker
28c6d60150
temporarily removing buildroot from regression until it is regenerated
2021-06-07 13:20:50 -04:00
David Harris
dc0b19dfaa
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Ross Thompson
41a1e6112a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-04 15:16:39 -05:00
Ross Thompson
7406e33b61
Continued I-Cache cleanup.
...
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
191f7e61fd
Moved I-Cache offset selection mux to icache.sv (top level).
...
When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Katherine Parry
fc65aedbd6
Double-precision FMA instructions
2021-06-04 14:00:11 -04:00
Ross Thompson
fdef8df76b
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
David Harris
0674f5506e
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
bbracker
4e765ee1c5
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
bbracker
846553ac7d
improved PLIC test organization
2021-05-21 15:13:02 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
1d3db5ead5
small bit of busybear debug progress
2021-05-19 20:18:00 -04:00
James E. Stine
304e70d3ae
Update rv64icfd batch script
2021-05-18 16:01:53 -05:00
David Harris
5da159d17e
Removed rv64wally
2021-05-18 14:08:46 -04:00
David Harris
4d264c6f61
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
bbracker
f00eb22700
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
2021-05-17 19:25:54 -04:00
bbracker
e4c90f503a
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
2021-05-17 18:44:47 -04:00
David Harris
9901f54b15
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
Elizabeth Hedenberg
b818ce608a
commit ehedenberg coremark
2021-05-17 18:02:35 -04:00
James E. Stine
3d3e3434f6
Cleanup of regression
2021-05-17 16:58:15 -05:00
James E. Stine
865b3ee219
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
6aa04af38d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-14 07:40:08 -04:00
Thomas Fleming
ea4e76938e
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Jarred Allen
041149eaf7
Minor fixes in regression
2021-05-09 13:57:09 -04:00
Jarred Allen
c7f400262c
Fix bug in regression script
2021-05-06 12:56:57 -04:00
Jarred Allen
be029ba02c
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
Thomas Fleming
ad40464557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
2d1d929485
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
463ba1a2be
coremark directory changes
2021-05-03 19:35:06 -04:00
Ross Thompson
82b4d42f32
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Thomas Fleming
ba1afec621
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Jarred Allen
7d509252a7
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
e145670b15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
19a93345b5
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
a54c231489
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
9ab714e636
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
c7b97d0339
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Noah Boorstin
48d32c1daf
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Thomas Fleming
6e5fc107d9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
4fae8088e3
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
ebd9c0ee29
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Thomas Fleming
c62fdfb7b3
Remove unused waves from .do files
2021-04-29 02:19:46 -04:00
