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Author	SHA1	Message	Date
David Harris	748375c82f	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
David Harris	21bdce63ff	Testgen working for Lab 2	2022-01-26 18:01:51 +00:00
David Harris	4d788505f2	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-26 17:21:09 +00:00
David Harris	e16982aeb0	New testgen.py	2022-01-26 17:21:02 +00:00
bbracker	676d4c5fa7	a different approach to QEMU: add Wally as a completely new machine	2022-01-26 15:02:24 +00:00
Ross Thompson	840e814e95	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-25 19:21:04 -06:00
Ross Thompson	d46bc94119	Added pin location for reset on VCU118 board. Somehow this was missing and still worked.	2022-01-25 17:48:42 -06:00
David Harris	3a7786877a	Removed and restored embench-iot	2022-01-25 22:12:28 +00:00
Ross Thompson	bb11f5637c	Added comport.setup to remind how to configure com port for xilinx fpga. ... Added load-deadlock.tsm to trigger load operation deadlock.	2022-01-25 14:54:38 -06:00
David Harris	8d04e83c9f	simpleram simplification	2022-01-25 19:46:13 +00:00
David Harris	9da1ed4ed9	simpleram simplification	2022-01-25 19:40:07 +00:00
David Harris	a86a9f5c2a	simpleram simplification	2022-01-25 18:26:31 +00:00
David Harris	e3136c9a1e	simpleram address simplification	2022-01-25 18:17:33 +00:00
David Harris	7ad2eb009a	simpleram address simplification	2022-01-25 18:00:50 +00:00
David Harris	6a555032eb	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
David Harris	cf50beb958	Start of IFU cleanup	2022-01-25 17:31:53 +00:00
David Harris	99a824fdc1	removed sum executable	2022-01-25 10:24:05 +00:00
David Harris	8d83b3b722	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-25 06:53:07 +00:00
David Harris	2bc7399ad4	More example Makefile cleanup	2022-01-25 06:53:03 +00:00
davidharrishmc	f6a27588f3	Update README.md	2022-01-24 15:47:42 -08:00
davidharrishmc	544b9273c2	Update README.md	2022-01-24 15:46:24 -08:00
David Harris	2dc73574d3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-24 23:21:16 +00:00
David Harris	12e08d8055	Fixed sumtest reference output; added embench benchmark directory	2022-01-24 23:21:09 +00:00
kaveh Pezeshki	b0cbe9dba8	added qemu patches in tests/linux-testgen/qemu	2022-01-24 07:52:07 +00:00
Ross Thompson	8ef70389d3	Added spill support back into the IROM IFU.	2022-01-21 15:50:54 -06:00
Ross Thompson	9982549057	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	0ceaf792ed	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-21 00:12:18 +00:00
David Harris	39d318fb2a	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
Ross Thompson	e2343699d1	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
David Harris	57f859a882	fir.c	2022-01-20 17:15:53 +00:00
David Harris	771c44698b	Added FIR example	2022-01-20 16:57:36 +00:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	cea09aab98	Removed imperas tests from makefile for now	2022-01-20 14:51:56 +00:00
David Harris	fc932ef0ff	Added top-level make clean	2022-01-20 14:17:26 +00:00
David Harris	d5f12195c8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-20 00:04:27 +00:00
David Harris	3005d82dba	Created linux directory for linux config	2022-01-20 00:04:23 +00:00
Ross Thompson	acec56c27e	Added PCNextF and PostSpillInstrRawF to ila.	2022-01-19 14:05:14 -06:00
Ross Thompson	c913a3ceeb	Fixed fpga ila debug to match lsu changes.	2022-01-18 21:13:18 -06:00
David Harris	9b29710990	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-19 00:26:34 +00:00
Ross Thompson	4a75e69457	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	28859f959b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-18 17:19:59 -06:00
Ross Thompson	a5f773220e	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	ebf9f5d526	riscvsingle reparittioned to match Ch4	2022-01-17 16:57:32 +00:00
David Harris	55b4423329	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	bd320c2f76	lsu cleanup down to 346 lines	2022-01-15 01:19:44 +00:00
David Harris	325724f556	LSU Cleanup	2022-01-15 01:11:17 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	fd13272d4c	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
David Harris	db2271b7e0	LSU cleanup	2022-01-15 00:11:30 +00:00