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Author SHA1 Message Date
Harshini Srinath
2d9006522a
Update ahbcacheinterface.sv 
Program clean up
 2023-06-10 18:15:53 -07:00
Harshini Srinath
2f47a6e04f
Program clean up 2023-06-10 18:13:40 -07:00
Ross Thompson
d6681b5342
Merge pull request #319 from davidharrishmc/dev 
Renamed Performance Counter extension
 2023-06-09 21:21:45 -04:00
David Harris
b20363f9c2 Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
5b0c539955
Merge pull request #318 from harshinisrinath1001/main 
Fixed the spacing of the cache module
 2023-06-09 17:00:53 -07:00
David Harris
9373ad3811 Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b15c5e2a51 Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
David Harris
d674c9b45c Other Wally cleanup 2023-06-09 09:37:09 -07:00
David Harris
e2e6f6f255 Added named support for Zicntr and Zihpm 2023-06-09 09:35:51 -07:00
Harshini Srinath
107ebf6a3c
Update ebu.sv 
Code clean up
 2023-06-09 08:53:27 -07:00
Harshini Srinath
b4e5f43acb
Update subcachelineread.sv 
Code clean up
 2023-06-09 08:50:51 -07:00
Harshini Srinath
7475a0eeed
Update cacheway.sv 
Code clean up
 2023-06-09 08:48:11 -07:00
Harshini Srinath
fcac659e34
Update cacheLRU.sv 
Code clean up
 2023-06-09 08:43:38 -07:00
Harshini Srinath
1f1fcce062
Update cache.sv 
Formatting clean up
 2023-06-09 08:39:57 -07:00
David Harris
35db95cc0c
Merge pull request #317 from ross144/main 
Updated parameterization types.  Modelsim version 2022.1 did requires defaults to a 32 bit integer.  The base and ranges for the address decoder need to be larger.
 2023-06-09 07:34:42 -07:00
Ross Thompson
c3102bb82b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-09 09:28:31 -05:00
Ross Thompson
9bae203d1c Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger. 2023-06-09 09:28:24 -05:00
David Harris
1c547fc02e
Merge pull request #316 from ross144/main 
Fixed garbled output in embench
 2023-06-08 09:09:13 -07:00
Ross Thompson
74ccabdf69 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
441ffc6d41
Merge pull request #315 from davidharrishmc/dev 
CoreMark runs without error after post processing script is removed
 2023-06-06 23:30:58 -04:00
David Harris
cea6f89ac8 Removed postprocessing script from Coremark because percentages are already computed 2023-06-06 20:12:13 -07:00
Ross Thompson
f4883e31df
Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
David Harris
09c8886f0d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-06 08:46:54 -07:00
David Harris
753ec9a11c Modified benchmarks/coremark/Makefile to clean addins/coremark as well 2023-06-06 08:46:44 -07:00
David Harris
62a8332c8f
Merge pull request #313 from ross144/main 
Fix extraneous force in testbench which keep btb in reset.
 2023-06-06 08:41:34 -07:00
David Harris
df212ce7d8
Merge pull request #312 from ross144/main 
Fixed typo in coremark makefile.
 2023-06-06 05:44:22 -07:00
Ross Thompson
822e60bd3d Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
21a73e0e43 Fixed typo in coremark makefile. 2023-06-05 11:49:16 -05:00
Ross Thompson
f9ca6732b8
Merge pull request #311 from stineje/main 
Update some bugs in FPU
 2023-06-05 12:19:08 -04:00
James Stine
736ae7d749 Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing 2023-06-05 11:03:59 -05:00
James Stine
51d77b0414 Update some spacing to make it look better 2023-06-05 11:03:06 -05:00
Ross Thompson
80cdb02d43 Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
7cd727c918 Oups forgot to include updates to the lint script itself. 2023-05-31 11:00:38 -05:00
Ross Thompson
e56497101a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
ab91fe7436 Cleanup parameterization for verilator 5.010. 2023-05-31 10:02:34 -05:00
David Harris
94629d0570 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-31 06:31:52 -07:00
David Harris
c1e7332abf Fixed paths in creating division test vectors 2023-05-31 06:30:41 -07:00
David Harris
436ba397ce Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
2232767bba
Merge pull request #307 from davidharrishmc/dev 
Assorted cleanup, including test vector generation
 2023-05-30 20:04:58 -04:00
David Harris
8c1bd8523a Clean up combined int/fp vector creation 2023-05-30 14:01:12 -07:00
David Harris
97763beb75 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:53:28 -07:00
David Harris
ca0b89c607
Merge pull request #306 from ross144/main 
fixed testfloat testbench for parameterization
 2023-05-30 13:53:14 -07:00
Ross Thompson
52b41b2050 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-30 15:51:19 -05:00
Ross Thompson
0f8049a04f Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
David Harris
0c718f2b71 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:40:56 -07:00
David Harris
1b647dc235
Merge pull request #305 from ross144/main 
Fixed all do scripts for parameterization
 2023-05-30 13:40:44 -07:00
Ross Thompson
bf65527b29 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-30 15:38:58 -05:00
Ross Thompson
e859609a6e Updated do files for parameterization. 2023-05-30 15:38:03 -05:00
David Harris
ed9a834bc1
Merge pull request #304 from ross144/main 
Fixes bug 203 and linux/ImperasDV mismatch at 571M instructions
 2023-05-30 13:37:00 -07:00
Ross Thompson
3c94c186db Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt. 
This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state.  Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state.  When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE.  There may still be a remaining bug here if the pipeline is stalled for another reason.  However I don't think it is possible by construction.  The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
 2023-05-30 15:20:24 -05:00