18 Commits

Author	SHA1	Message	Date
James Stine	b9480a4643	Added the 12T submodule to the project.	2022-02-03 19:26:41 -06:00
David Harris	069f270d1a	Removed soc_flow	2022-01-31 22:58:33 +00:00
David Harris	c367d19fc6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-31 00:59:49 +00:00
David Harris	ea85e185f1	gitmodules	2022-01-31 00:59:44 +00:00
James Stine	ef811c7786	Remove book_flow to add back later - will add synthDC back within 30m	2022-01-28 08:18:30 -06:00
David Harris	384cd0d092	Added synthesis submodules	2022-01-27 14:31:34 +00:00
David Harris	de7b9c127e	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	e25760d8e5	Added C test cases	2022-01-11 21:01:48 +00:00
David Harris	07f34c8263	.gitmodule added dirty riscv-arch-test	2021-12-29 23:50:17 +00:00
David Harris	e97e512da9	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
David Harris	434f49c03e	Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead	2021-12-21 02:35:41 +00:00
Kevin Kim	869cd44533	added arch-test submodule	2021-11-30 18:22:08 -08:00
Kevin Kim	6323609da9	Added git submodules ... -riscv-arch-test -rscv-isa-sim submodules are added in addins/ directory	2021-11-30 18:16:37 -08:00
kipmacsaigoren	b2677d2090	Added git things to make it all a little nicer and synthesis work.	2021-09-15 12:15:53 -05:00
Teo Ene	1d5d7a7840	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
Teo Ene	bd99a5613a	sky130 18T and 15T cell libraries removed ... Upon noticing their size, concerns were raised about available drive space. As 12T is the main implementation focus, the decision was made to remove 15T and 18T. Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.	2021-02-14 09:05:41 -06:00
Teo Ene	af3a888cde	Removed riscv-o3 module	2021-02-12 16:08:34 -06:00
Teo Ene	a54070d074	Added synth and PnR flow	2021-01-25 14:28:14 -06:00