4 Commits

Author	SHA1	Message	Date
Ross Thompson	3d829dbbd3	Fixed two issues. ... First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards.	2021-12-07 12:15:50 -06:00
Ross Thompson	41258529f0	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00
Ross Thompson	6a228ade04	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	96926877c4	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00