39 Commits

Author	SHA1	Message	Date
David Harris	aa7b0616e4	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
David Harris	788fe406b5	Moved delegation logic from privmode to trap to simplify interface	2022-05-31 14:58:11 +00:00
David Harris	48e89485dd	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	9651ced9bb	Cause simplification	2022-05-12 23:39:10 +00:00
David Harris	5b7cccbc4b	Cause simplification	2022-05-12 23:33:22 +00:00
David Harris	c2b9fc0d8e	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	292d1f33da	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	662fffa830	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	16b86c199c	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	5f358a37c6	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	21ac969c7d	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	072c464dc1	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	dd61afb7dc	Formatting cleanup	2022-05-12 18:37:47 +00:00
David Harris	5670f77de2	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	4edf9b6355	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	e2e63ca9a8	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	4f1b0fdc64	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	1a5bfcf078	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	a516f89f22	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	28e8aa4f97	Fixed InstrMisalignedFaultM mtval	2022-04-24 17:31:30 +00:00
David Harris	ffecdda6e6	Improved priority order and mtval of traps to match spec	2022-04-24 17:24:45 +00:00
Kip Macsai-Goren	bd87af478a	Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)	2022-04-22 22:46:11 +00:00
David Harris	b4902a6ff9	First implementation of WFI timeout wait	2022-04-17 17:20:35 +00:00
Ross Thompson	de868ef3a2	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
bbracker	69a0f6e00b	big interrupts refactor	2022-03-30 13:22:41 -07:00
David Harris	c4f2c6b110	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Kip Macsai-Goren	709f8e6e0d	fixed double multiplication on vectored interrupts	2022-03-28 19:12:31 +00:00
David Harris	72e83db9fe	removed csrn and all of its outputs because depricated	2022-02-15 19:59:29 +00:00
David Harris	d3034c4f01	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
David Harris	f734afb866	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
Ross Thompson	06209c417f	Cleaned up the InstrMisalignedFault.	2022-01-28 13:19:24 -06:00
Ross Thompson	862bf2faae	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
Ross Thompson	e06fb923a1	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
Ross Thompson	b294f1fbb0	Oups. My hack for DivE interrupt prevention was wrong.	2022-01-12 14:17:16 -06:00
Ross Thompson	459f4bd3b4	Hack "fix" to prevent interrupt from occuring during an integer divide. ... This is not the desired solution but will allow continued debuging of linux.	2022-01-12 14:17:16 -06:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00