15 Commits

Author	SHA1	Message	Date
David Harris	1e7401daa0	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
David Harris	9999f69922	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	4f1b0fdc64	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	1a8369b02b	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	142636173e	Added MTINST hardwired to 0, and added timeout of U-mode WFI	2022-04-24 20:00:02 +00:00
Ross Thompson	19a8df9739	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	69a0f6e00b	big interrupts refactor	2022-03-30 13:22:41 -07:00
David Harris	d3034c4f01	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
David Harris	02071700d6	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	e2343699d1	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	4a75e69457	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	a5f773220e	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00